Designer's Notebook

September 03, 2026

Designers Notebook: Implementing Strategic Planning Principles for PCB Design

Developing multiple-processor system-level products involves a broad range of engineering disciplines (commonly referred to as co-design), often led by a designated program manager who divides the development program into technical disciplines. The primary member of this team is the electrical engineer (EE), who prepares the overall schematic diagram of the product. This effort includes simulation and modeling, developing a BOM, and defining all active components and any specialized passive elements (often stipulating preferred or prequalified sources).

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July 08, 2026

Designers Notebook: Old vs. New School System-level Packaging—Flip-Chip to Chiplets

The electronics industry has experienced a renaissance in semiconductor package technology, driven by the need to maximize electronic product functionality while minimizing the area reserved for component mounting and interconnects. Passive surface mount components are relatively small, while the packaged semiconductor die is significantly larger than the tiny die element it encases. The plastic-packaged semiconductor, although suitable for use on PCBs, is far too bulky for those developing electronics that require miniaturization: new product introduction systems for physically stressful operating conditions, such as aeronautics, military ordinance, and space missions.

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March 16, 2026

Designers Notebook: Heterogeneous Interposer Design Challenge, Part 3

In just about any industry, time-to-market will establish the difference between the leaders and followers. Any new electronic product introduced into the market must meet or exceed stated performance criteria and provide reliable service to the end user experience. The original single-core monolithic system-on-chip developed for the earlier, less complex applications has long been superseded by the more sophisticated multiple-core variations.

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February 16, 2026

Designers Notebook: Heterogeneous Interposer Design Challenge, Part 2

As the need grows for higher processing speed and the expanded functionality required for newer generations of central processing units (CPUs), the necessity for higher-density interconnect solutions is paramount. The current trend toward furnishing a single, monolithic system-level semiconductor package has become a serious yield issue in fabrication. For example, with all of the peripheral supporting functions on a single die platform, wafer fabrication yields are often below target and, although the CPU portion of a monolithic semiconductor may be perfect, if one or more of the supporting functions on the same die fails, the entire processor unit must be discarded. 

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January 19, 2026

Designers Notebook: Heterogeneous Interposer Design Challenge, Part 1

The development of monolithic (system-on-chip) ICs revolutionized the electronics industry, enabling the creation of heterogeneous products by integrating multiple active elements within the same silicon base, which includes a central processing unit (CPU), memory functions, sensors, and communication tasks.

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October 29, 2025

Designers Notebook: Power and Ground Distribution Basics

The principal objectives to be established during the planning stage are to define the interrelationship between all component elements and confirm that there is sufficient surface area for placement, the space needed to ensure efficient circuit interconnect, and to accommodate adequate power and ground distribution.

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July 22, 2025

Designers Notebook: Basic PCB Planning Criteria—Establishing Design Constraints

Printed circuit board development flows more smoothly when all critical issues are predefined and understood from the start. As a basic planning strategy, the designer must first consider the product performance criteria, then determine the specific industry standards or specifications that the product must meet. Planning also includes a review of all significant issues that may affect the product’s manufacture, performance, reliability, overall quality, and safety.

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April 17, 2025

Designers Notebook: Layer Stackup Planning for RF Circuit Boards

When designing multiple layer circuits requiring impedance control, the circuit board designer will work closely with an engineering specialist cognizant of RF printed circuit board design and layout, including mixed-signal applications.

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February 06, 2025

Designers Notebook: Addressing Future Challenges for Designers

The printed circuit board is and will probably continue to be the base platform for most electronics. With the proliferation of new generations of high I/O, fine-pitch surface mount semiconductor package variations, circuit interconnect is an insignificant factor. Circuit board designers continually face challenges such as component quantity and complexity, limited surface area, and meeting the circuit board’s cost target. The printed circuit design engineer’s prominent position demands the development of efficiently manufacturable products that perform without compromise.

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January 07, 2025

Designers Notebook: Impact of Advanced Semiconductor Packaging on PCB Stackup

To accommodate new generations of high I/O semiconductor packaging, printed circuit board fabrication technology has had to undergo significant changes in both the process methods and the criteria for base material selection and construction sequence (stackup). Many of the new high-function multi-core semiconductor package families require more terminals than their predecessors, requiring a significantly narrower terminal pitch. Interconnecting these very fine-pitch, high I/O semiconductors to the PCB is made possible by an intermediate element referred to as an interposer.

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October 23, 2024

Designers Notebook: Implementing HDI and UHDI Circuit Board Technology

To accommodate new generations of high I/O semiconductor packaging, circuit board technology has undergone significant changes in both the fabrication process method and the criteria for base material selection. The reason behind these changes is the new high-function semiconductor package families that require more terminals than their predecessors and a significantly narrower terminal pitch.

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October 03, 2024

Designer's Notebook: Heterogeneous Integration and High-density SiP Technologies

Often, our primary goal is to maximize product functionality without increasing product size. Developing a multifunction silicon-based semiconductor (system-on-chip) for a specific product application, however, requires a significant investment in both engineering and financial resources. The problem is that many of the newer generations of semiconductor die have actually increased in size, with higher I/O and terminal pitch variations that have become significantly smaller.

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August 06, 2024

Designers Notebook: PCB Design and IPC-CFX for Assembly Automation

Surface mount technology (SMT) is a manufacturing process that, through the application of a wide range of small outline components, provides capability to design a printed circuit with higher component density. The assembly process offers the user a means of efficiently producing electronic products in high volume with robotic assembly processing. The circuit board designer can serve a vital role in developing a surface mount configured product that will be prepared for efficient assembly processing.

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April 24, 2024

Designer’s Notebook: What Designers Need to Know About Manufacturing, Part 2

The printed circuit board (PCB) is the primary base element for providing the interconnect platform for mounting and electrically joining electronic components. When assessing PCB design complexity, first consider the component area and board area ratio. If the surface area for the component interface is restricted, it may justify adopting multilayer or multilayer sequential buildup (SBU) PCB fabrication to enable a more efficient sub-surface circuit interconnect.

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January 25, 2024

Designers Notebook: What Designers Need to Know About Manufacturing, Part 1

The designer needs to have a working understanding of two key manufacturing operations: basic circuit board fabrication procedures and assembly process practices. For printed circuit board manufacturing, the number of steps required to produce the printed circuit board correlates to the circuit board's complexity. Greater process complexity in fabricating the circuit board equates to increased costs. To develop any portion of the electronic product, the designer must apply the design for manufacturing (DFM) principles established in the industry. In fact, DFM should always be the goal of the design engineer. It encompasses a wide range of disciplines that must be considered during the planning phase of any product.

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September 14, 2023

Designer’s Notebook: DFM Principles for Flexible Circuits

Flexible circuit applications can be as basic as furnishing electrical interconnect between two conventional circuit board assemblies, or to prove a platform for placing and interconnecting electronic components. During the planning and pre-design phase of the flexible circuit, there will be several material and process related questions that need to be addressed. Most flexible circuit fabricators welcome the opportunity to discuss their customers’ flexible circuit objectives prior to beginning the actual design process.

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August 01, 2023

Designers Notebook: PCB Designers Guide to Heterogeneous Chiplet Packaging

Integrating multiple chiplet elements on a single interposer or package substrate may be referred to as a multi-chip module, a hybrid IC, a 2.5D package or simply an advanced package. Implementing chiplet technology will provide several advantages over the traditional, system-on-chip alternative: Each chiplet element is designed to be a building block with a specific function that is often common for multiple system-level products. Chiplet elements can also be sourced from multiple providers, even though they may be using alternative fabrication processes.

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March 22, 2023

Designer's Notebook: PCB Design for Bare Board Testing

There are several testing methods used for certifying that the circuit board meets its defined quality level and intended functional criteria. Multilayer circuit boards have become increasingly complex: finer conductor line definition, blind and buried microvia interface, and smaller, finer-pitch SMT land pattern geometries. Visual assessment using automated optical inspection (AOI) is adopted to check all circuit layers prior to lamination and as a final examination of the end product.

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January 20, 2023

Designers Notebook: Flexible Circuits for In-line SMT Assembly Processing

Incorporating surface mount components directly onto a flexible circuit’s etched copper land patterns is not unlike the assembly process used for rigid circuit boards. To maximize robotic assembly efficiency and increase throughput of the flexible circuit, however, the circuit design engineer will need to provide a format that includes all features required for in-line assembly processing.

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November 03, 2022

Designers Notebook: Ultra High-Density Circuit Board Design

To facilitate new generations of high I/O semiconductor packaging, circuit board technology is undergoing significant refinement in both fabrication process methods and base materials selected. Many of the new high-function semiconductor package families require significantly more terminals than their predecessors. Interconnecting these very fine-pitch, high I/O semiconductors can dramatically affect the procedures used in both circuit board design and assembly processing.

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May 04, 2022

Designers Notebook: Design for Test, Part 3

The general trend in electronics is to improve performance and minimize product size, often leading to more complex printed circuit board and higher component density. Semiconductor packaging in particular, have become more complex, many having multiple functions interconnected within the package or onto the silicon itself. For products with very high component density companies soon realize that 100% test-probe access may not be possible.

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March 07, 2022

Designers Notebook: A Lesson on Automated Optical Shaping

IPC APEX EXPO show and conference was safely back in full swing after skipping 2021. Because my primary interest is printed circuit board and assembly processing, I ventured onto the show floor to review some of systems exhibited that have evolved that may contribute to process efficiency and end product quality. A key benefit of attending a show like this one is that the board and assembly manufactures can view and compare similar product offerings in one place.

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March 08, 2022

Designers Notebook: Design for Test, Part 2

Current generations for PCB designs have increased in complexity. The product developer and assembly service provider, whether in-house or outsourced, must consider manufacturing efficiency, throughput, and process yield. While design for manufacturing is an absolute necessity for controlling manufacturing costs, design to accommodate product testing does need attention as well. The primary concern is to ensure that the end product will perform reliably without compromise.

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February 03, 2022

Designer's Notebook: Design for Test, Part 1

Circuit board fabricators remind us that multilayer boards will predictably have more components necessitating greater circuit routing complexities than that experienced on earlier applications. Also, with each generation of semiconductors it seems that the terminal count increases and the spacing between terminals shrinks, requiring designers to employ conductor lines and spaces that are far narrower than previously considered the norm.

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June 15, 2021

Designers Notebook: Embedding Resistor Elements—Part 2

As an alternative to the thick-film resistor process detailed in Part 1, a significant number of PCB fabricators are offering embedded thin-film resistor capability. Read Part 2 here.

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April 19, 2021

Designers Notebook: The 'New and Growing' Embedded Resistors

Why is embedded resistor technology considered to be “new” and “growing” despite decades of history? In fact, a broad number of established PCB fabricators are knowledgeable about the materials and processes for embedding resistor elements but not all may be prepared to alter procedures established for their more conventional multilayer circuit board customer base.

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February 22, 2021

Designers Notebook: Developing Panel Level Semiconductor Packaging

While semiconductor packaging has traditionally utilized a narrow strip of organic copper-clad organic-based laminate and wire-bond processing for the single-die BGA. Companies furnishing devices for high-volume markets are now implementing very fine-pitch alloy bumped flip-chip package technologies that enable face-down interface.

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May 15, 2020

Designers Notebook: Panel-level Semiconductor Package Design Challenges

Semiconductor package specialists continually work to improve high-volume manufacturing process efficiencies while reducing manufacturing costs. A majority of the commercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. Vern Solberg explains.

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January 15, 2020

Designers Notebook: PCB Design and HD Semiconductor Packaging

To better meet their performance and miniaturization goals, manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. Vern Solberg covers how this and more impact PCB design and HD semiconductor packaging.

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January 29, 2020

Designers Notebook: Design Challenges for Developing High-density 2.5D Interposers, Part 2

In Part 2 of his column series on design challenges for high-density 2.5D interposers, Vern Solberg discusses primary base materials for 2.5D interposer applications, design guidelines, technical challenges, and key planning issues.

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October 03, 2019

Designers Notebook: Focus of Interest at SMTAI 2019—Low-temperature Solder

Both suppliers and users of solder materials participated in discussions at SMTAI 2019 related to low-temperature solder (LTS). The solder supply companies present had a wide range of material compositions that employed elements of bismuth or indium to reduce the liquidus temperature of the alloy during the joining process. Key issues that user companies are concerned with are the lower-temperature alloys selected must be reliable and exhibit shear strength, creep resistance, and resistance to thermal fatigue for the duration of the product’s life cycle.

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March 11, 2019

Designers Notebook: Embedding Components, Part 7—Semiconductor Placement and Termination Methodologies

Progress in developing high-density embedded-component substrate capability has accelerated through the cooperation and joint development programs between many government and industry organizations and technical universities. In addition to these joint development programs, several independent laboratories and package assembly service providers have developed a number of proprietary processes for embedding the uncased semiconductor elements.

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January 10, 2019

Embedding Components, Part 6: Preparation for Active Semiconductor Elements

Designers are well aware that a shorter circuit path between the individual die elements, the greater the signal transmission speed, which significantly reduces inductance. By embedding the semiconductors on an inner layer directly in line with related semiconductor packages mounted on the outer surface, the conductor interface distance between die elements will be minimized.

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December 19, 2018

Embedding Components, Part 5: Alternative Termination Methodologies and Surface Plating Variations

Because they are furnished with a very thin profile, resistor and capacitor components with different values can be mounted directly onto land patterns on a subsurface layer of the printed circuit structure. However, handling and placing of these small components requires systems with a high level of positional accuracy. Interconnection can be accomplished using either deposited solder paste and reflow processing or applying a conductive polymer material. Due to the extremely small land pattern geometries required for mounting the miniature passive components, companies commonly rely on precision dispensing these materials.

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November 29, 2018

Embedding Components, Part 4: Passive Component Selection and Land Pattern Development

As noted in Part 3 of this series, a broad range of discrete passive component elements are candidates for embedding, but the decision to embed these component elements within the multilayer circuit structure must be made early in the design process. While many of these components are easy candidates for integrating into the substrate, others may not be suitable, or they are difficult to rationalize because they involve more complex process methodology.

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November 15, 2018

Embedding Components, Part 3: Implementing Discrete Passive Devices

Most of the passive components used in electronics are discrete surface mount components configured to mount onto land patterns furnished on the surface of a PC board. Designers have several choices for providing passive functions in a system design, such as discrete surface-mounted passives, array passives or passive networks, integrated (Rs and Cs) passive devices, and embedded discrete passive components.

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July 30, 2017

Embedding Components, Part 2

Technology and processes for embedding capacitor and inductor elements rely on several unique methodologies. Regarding providing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate-based (copper-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials.

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June 30, 2017

Embedding Components, Part 1

The printed circuit has traditionally served as the platform for mounting and interconnecting active and passive components on the outer surfaces. Companies attempting to improve functionality and minimize space are now considering embedding a broad range of these components within the circuit structure. Both uncased active and passive component elements are candidates for embedding but the decision to embed components within the multilayer circuit structure must be made early in the design process.

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January 01, 2018

Designers Notebook: Strategies for High-Density PCBs

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as HDI processing. The primary driver for HDI is the increased complexity of the more advanced semiconductor package technology. These differences can be greater than one order of magnitude in interconnection density.

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November 27, 2017

Strategies for High-Density PCBs

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as high-density interconnect (HDI) processing.

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July 06, 2016

Specifying Lead-Free Compatible Surface Finish and Coating for Solderability and Surface Protection

A majority of the components furnished for electronic assembly are designed for solder attachment to metalized land patterns specifically designed for each device type. Providing a solder process-compatible surface finish on these land patterns is vital...

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May 26, 2016

Flexible and Rigid-Flex Circuit Design Principles, Part 6

The designer is generally under pressure to release the documentation and get the flexible circuit into production. There is, however, a great deal at risk. Setting up for medium-to-high volume manufacturing requires significant physical and monetary resources. To avoid potential heat from management, the designer must insist on prototyping the product and a thorough design review prior to release.

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April 27, 2016

Flexible and Rigid-Flex Circuit Design Principles, Part 5

The outline profile of the flexible circuit is seldom uniform. One of the primary advantages of the flexible design is that the outline can be sculpted to fit into very oblique shapes. In this column, Vern Solberg focuses on outline planning, physical reinforcement, and accommodating bends and folds in flexible and rigid-flex circuits.

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March 30, 2016

Flexible and Rigid-Flex Circuit Design Principles, Part 4

All of the design rules for the glass reinforced-portion of the board (land pattern geometry for mounting surface mount devices, solder mask and the like) are now well-established. One unique facet of fabricating the rigid-flex product is how the flexible portion of the circuit is incorporated with the rigid portion of the circuit. As a general rule for multilayer PCB design, furnish a balanced structure by building up the circuit layers in pairs (4, 6, 8 and so on).

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March 02, 2016

Flexible and Rigid-Flex Circuit Design Principles, Part 3

This column focuses on methods for specifying base materials, and also address copper foil variations and fabrication documentation. It is important to research the various products in order to choose the one that best meets the design requirements.

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February 19, 2016

Flex and Rigid-Flex Circuit Design Principles, Part 2

Flexible circuits are commonly developed to replace ordinary printed circuit board assemblies that rely on connectors and hardwire for interconnect.

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January 27, 2016

Flex and Rigid-Flex Circuit Design Principles, Part 1

Flexible circuits represent an advanced approach to total electronics packaging, typically occupying a niche that replaces ordinary printed circuit board assemblies and the hard-wire interface needed to join assemblies.

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January 03, 2005

PCB Designers Notebook: Flexible Circuit Design

The flexible circuit was originally used as a conductive element for interfacing signals from one electronics assembly to another.

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