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Designers Notebook: Old vs. New School System-level Packaging—Flip-Chip to Chiplets

The electronics industry has experienced a renaissance in semiconductor package technology, driven by the need to maximize electronic product functionality while minimizing the area reserved for component mounting and interconnects.

Passive surface mount components are relatively small, while the packaged semiconductor die is significantly larger than the tiny die element it encases. The plastic-packaged semiconductor, although suitable for use on PCBs, is far too bulky for those developing electronics that require miniaturization: new product introduction systems for physically stressful operating conditions, such as aeronautics, military ordinance, and space missions.

For these applications, design engineers needed to abandon the plastic-encapsulated lead-frame-packaged semiconductor and use only bare, uncased die elements. So, companies began to quickly and economically develop modular hybrid system-level products with commercially available uncased die, implementing the same assembly methods used for packaged semiconductors and wire-bond technology. This category of products became known as a multi-chip module (MCM).

What is a Multi-chip Module?
This generic electronic assembly method integrates two or more bare (uncased) semiconductor die and related discrete components onto a common substrate or interposer platform to provide interconnect. The MCM wire-bond assembly sequence begins with die-attach, the placement of the die onto an adhesive deposited on the substrate's surface, with the active surface of the die facing up. Wire-bond processing follows, connecting the terminal sites on the die element to land pattern features located on the substrate's surface. Following wire-bond, the die and wire are coated with a liquid polymer material that, when cured, protects the die and delicate wire interconnects from physical disturbance.

The wire-bond process uses extremely fine-diameter wires (≤ 40 microns or 0.0015"), typically made of soft metals such as gold, silver, or aluminum.

The classic MCM variations are assembled onto a metallized, ceramic-based substrate (Figure 1), a dielectric material that closely matches the CTE of the silicon die elements and exhibits excellent thermal conductivity.

Other variations may use glass-reinforced FR-4 or polyimide dielectrics as a base platform. The fabrication processes for these materials enable multiple-layer construction and, when employing a semi-additive copper plating process, very high interconnect density at a moderate fabrication cost. 

Flip-chip Packaging
As an alternative to wire-bond processing, many companies opted to adopt a process to terminate the die in a face-down orientation known as flip-chip. The face-down process was originally introduced commercially by IBM in the 1960s, using high-lead solder to form a raised terminal at each wire-bond site. The original IBM concept employed very small diameter solder-coated copper spheres placed on the lands originally furnished for wire-bond processing. In 1969, IBM replaced the copper-core spheres with solder-alloy bumps, as shown in Figure 2. 

The solder material proved to be more economical, easy to deposit, and compatible with the SMT assembly process:

• Print or deposit solder paste onto the land pattern.
• Place components.
• Employ a heating system to melt the solder to enable the joining of the component terminals to their respective land patterns on the substrate.

As the molten alloy begins to cool during the joining process, the alloy bumps collapse slightly, reducing the standoff height between the die and substrate surface. For the initial solder-bumped die process, IBM adopted C4 (Controlled Collapse Chip Connection) technology.

The increased component density enabled by multiple uncased die elements on a single interposer can significantly reduce the complexity of the host PCB. Close coupling between active devices will minimize power consumption and improve functional performance. It’s not uncommon to include discrete passive components (resistors and capacitors) on the same surface using the reflow solder processing for termination noted above.

In flip-chip packaging, the smallest possible package is always the size of the chip itself.

As the industry moved more toward miniaturizing semiconductor packaging in the mid-1990s, standards for chip-size and chip-scale packaging (CSP) began to evolve. Among the categories defined were fine-pitch BGA, die-size BGA, and wafer-level BGA (WLBGA), in which terminal forming occurs while die elements remain in wafer format.

Fan-in Wafer Level Packaging
The WLBGA is a type of BGA in which the finished component's outline is the individual die element. Terminal features required for attaching the semiconductor to a package substrate or circuit board are completed while the die elements remain in the wafer-level format. Developers may prepare the original wire-bond sites for direct chip attachment or use an additive copper plating process to redistribute the edge-located wire-bond sites to a more uniform array pattern. The additive metallization process (Figure 3) provides an electrically conductive interface from the wire-bond lands on the die element’s perimeter to a wider spaced and more uniform array-configured terminal pattern.

Fan-out Wafer Level Package
Fan-out wafer-level BGA represents a major evolutionary direction in packaging technology when the die element is not capable of providing enough area to accommodate all the I/O terminals within the device outline. In preparation for the fan-out WLP, a silicon wafer is developed to redistribute the very fine-pitch bond sites of the die element outward to a wider-array terminal pattern that is more compatible with conventional circuit board fabrication. Microvia through-holes are formed in the silicon (TSV) and Cu-plated to transfer the interconnect on the upper surface to an identical array pattern on the opposite surface.

Individual die elements are then placed face-down onto and joined to the silicon wafer surface. While remaining in the wafer format, the developer will often encapsulate the die with a molding compound to reinforce and protect the die elements, followed by the formation of terminals (solder balls, microbumps, or micropillars) on the wafer’s bottom surface. Finally, marking is applied, and each section is separated (sawing, laser) from the wafer format.

2.5D Package Integration
As semiconductor dies became more functionally complex, and the bump size and pitch continued to shrink, developers needed to adopt higher-density interconnections, moving from the traditional C4 solder ball or bumped terminal to a smaller solid-copper micro-pillar terminal that can support finer pitches and better electrical performance and mechanical stability. A wide range of semiconductor package innovations has already been developed to meet the growing proliferation of ultra-fine-pitch multicore processors and related semiconductors.

System-in-package developers have realized that, instead of the traditional monolithic integration used for earlier, less complex applications, adopting mature, high-yield miniature semiconductor chiplet-configured die to meet system-level criteria is more economical and can significantly reduce development time.

“Chiplets” is where old-school flip-chip packaging reemerges to become new-school technology. A chiplet is an integrated circuit block specifically designed to work with other similar chiplets. That is, by clustering and interconnecting two or more associated heterogeneous or homogenous semiconductor dies within the confines of a single package outline, closer coupling and the potential for enhanced electrical performance are enabled. By positioning these smaller, less complex functional chiplets in close proximity to the more advanced core processor die, as shown in Figure 4, interconnect distance is minimized and power and ground distribution are optimized.

Overall, the circuit density of the 2.5D interposer is significantly greater than that of the mainstream HDI circuit board. Commercial CAD tools are available to support most very high density (VHD) interposer development. The key enabler for success in chiplet packaging is the interposer. Acting as an intermediary, it furnishes a bridge for electrical signals and thermal management. While the upper surface of the 2.5D interposer accommodates a majority of the semiconductor redistribution and/or die-to-die interface, the primary I/O channels and power and ground terminals are located on the bottom surface of the interposer.

Furthermore, separating the pre-tested chiplet support functions from the core processor has improved process efficiency and maximized overall end-product yields; however, the shrinking of terminal size and pitch has become extreme. As the terminal features become narrower, solder process defects increase: opens, shorts, and bridging. Ideally, traditional solder processing can be avoided.

Hybrid Bonding
Hybrid bonding is a heterogeneous or homogeneous direct-bond interconnect technology that enables vertical joining of very fine-pitch semiconductor die-on-die, die-on-wafer, and even wafer-on-wafer without the use of solder or other additive conductive materials between the attached die surfaces. This technology is increasingly used to vertically join a wide range of semiconductor devices, including sensors, memory, and logic die elements. Contrary to all traditional packaging technologies, where the interconnects are joined first, then an underfill is inserted to occupy the space between the interconnects, the direct bond interconnect¹ process (hybrid interconnect) does not use solder or flux and does not require underfill between opposing surfaces.

Die bond interconnect is an enabling low-temperature, low profile die-to-wafer and die-to-die hybrid bonding technology platform. By eliminating the need for copper pillars and underfill, the process enables a dramatically thinner stack as compared to conventional approaches, allowing the stacking of die that are the same or different sizes, processed on fine or coarse wafer process technology nodes, or manufactured on the same or different wafer sizes while readily scaling down to 1 µm interconnect pitch. The opposing copper terminal surfaces are first aligned to one another and brought together. Alignment for this unique joining process is critical. The developer has stated that the current alignment accuracy of flip-chip bonders is in the 1–10 μm range.

Interconnection is completed using a moderate batch anneal, where the Cu bond pads expand to form a homogeneous metallic interconnect with grain growth across the bond interface. The chemical bond between oxides is significantly strengthened, ensuring high reliability.

Note: From a historical perspective, integration of multiple functional elements onto a single monolithic platform has become commonplace, although they prove most practical for high-volume applications. Monolithic integrated circuits are electronic circuits that consist of transistors, resistors, and diodes, and their connections, formed on the surface of a single piece of silicon, resulting in a seamless system-level structure. Developing these ASIC products often requires a great deal of engineering resources, monetary commitment, and time. Although many hybrid circuits can be replicated and produced as monolithic integrated circuits, it may not be economically feasible unless large quantities are required in the long term.

References

1. In 2015, Tessera Technologies, an Adeia member company in Santa Clara, California, acquired Ziptronix and added the oxide-bond process to its DBI IP portfolio. 

This column originally appeared in the June 2026 issue of I-Connect007 Magazine.