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Designers Notebook: Heterogeneous Interposer Design Challenge, Part 2

In part two of this series, current solutions and design guidelines will be furnished for preparing the interposer platform for interconnecting high-density, multiple core processor die and related miniature chiplet components.

As the need grows for higher processing speed and the expanded functionality required for newer generations of central processing units (CPUs), the necessity for higher-density interconnect solutions is paramount. The current trend toward furnishing a single, monolithic system-level semiconductor package has become a serious yield issue in fabrication. For example, with all of the peripheral supporting functions on a single die platform, wafer fabrication yields are often below target and, although the CPU portion of a monolithic semiconductor may be perfect, if one or more of the supporting functions on the same die fails, the entire processor unit must be discarded. 

Developers have found that the solution to this yield issue is to simply separate the more complex processor elements and the less complex functional support semiconductors and employ an interposer to furnish the interconnect. As the example in Figure 1 shows, by separating the processor(s) and memory functions into separate “chiplet” elements, the developer can rapidly create a system-level product using a silicon- or glass-based interconnect platform. 

The chiplet die are designed with micro-bumps, micro-posts or, for direct bond interconnect, an array of copper lands for direct, face-down termination. Until recently, chiplet-on-silicon interposers have been designed and manufactured offshore (Taiwan, Japan, Korea, and China), but there is growing industry support for reshoring semiconductor package technology.

For example, NVIDIA's Blackwell GPU silicon elements are now fabricated in TSMC’s facility in Phoenix, Arizona (Figure 2). To make a finished NVIDIA system-in-package product, however, the wafers or die elements must be transported back to the TSMC Taiwan facility, where they integrate the memory and other supporting functions using their chip-on-wafer-on-substrate process.   

This back-and-forth transfer of package processing, however, wastes precious time. If the end product is delayed by unexpected political or environmental factors, the anticipated delivery will be affected. The fact is, the capability for design and fabrication of the interposers already exists domestically. Additionally, assembly and joining technologies for die-on-wafer (D2W), and die-on-die stacking (D2D) are already mature processes that were actually developed by U.S.-based enterprises.

Note: NVIDIA Blackwell-architecture GPUs have 208 billion transistors and are manufactured using a custom-built TSMC 4NP process. All NVIDIA Blackwell products feature two reticle-limited dies connected by a 10 terabytes-per-second (TB/s) chip-to-chip interconnect in a unified single GPU.

Interposer Development
The primary purpose of an interposer is to facilitate the integration of multiple semiconductor elements (chiplets) onto a single silicon or glass-based platform. The process enables design flexibility and close coupling between related functions, potentially enhancing end package performance. The upper surface of the interposer accommodates the majority of semiconductor die-to-die interfaces; the primary I/O channels and power and ground terminals are positioned on the opposite surface. Although the overall circuit density of the interposer is significantly greater than the mainstream HDI circuit board, commercial CAD tools are available to accommodate most very-high-density system-in-package applications. While a majority of the die-to-die interconnects will be accomplished through a metallized pattern on the upper surface of the interposer, the primary I/O channels and the power and ground terminals will be transferred to the interposer’s bottom surface through the plated and filled microvia holes. 

Key Issues for Multiple Die Interposer Packaging 
Assembly process methodologies can vary a great deal, and several key issues will need to be resolved prior to beginning interposer design:

• Selection of suitable semiconductors for multiple die packaging
• Establishing sources for semiconductor wafers or pre-bumped die
• Specifying the environmental operating conditions
• Defining package design constraints and process protocols
• Stipulating electrical test method and post assembly inspection criteria

A note of caution: Although the individual die elements may continue to be furnished with a uniform terminal format, the die element outline, terminal size, and pitch may shrink. The changes may be to correct a defect or improve yield, but often the redesign is to reduce the die outline to enable a higher die population on the silicon wafer. If even a single die outline and/or terminal pattern is changed, a new interposer design will need to be developed.

Alternative Base Material for Chiplet Interposers

Although silicon-on-silicon package technology has reached a level of maturity, there are alternative materials that may be considered for specific applications. The three primary base materials commonly selected for interposer fabrication are ultra-low CTE epoxy-glass laminate, silicon, and glass.

Epoxy-glass-based organic composites

An ideal material for moderate density interposers or package substrates, the dielectric can range in thickness between 400 and 800 microns and is processed using a semi-additive copper plating process to furnish die-to-die interconnect. A typical organic-based interposer (or package substrate) will include a four-layer base and may have an additional one or two sequential build-up circuit layers for interconnect. Via-hole diameters can be as small as 50 microns, typically formed using laser ablation technology and filled with copper prior to final circuit imaging and chemical etching processes. 

Silicon-based interposer material

This is commonly furnished as a thin round wafer or a rectangular panel sized to comply with the existing semiconductor fabrication infrastructure. Metal deposition processes developed for the silicon-based interposer enable very close coupling between related die elements. The via-hole features on the die-attach side of the interposer may have a pitch in the range of 10-50 microns. Terminal features on the bottom surface are commonly “fanned-out” to a wider 150 to 300-micron pitch to enable silicon-to-substrate joining. The most common through-silicon-via (TSV) formation process uses a deep reactive-ion etching (DRIE) process (often referred to as the Bosch process) that can provide vias that range between 5 microns and 20 microns. 

Glass-based interposer material

Material developed specifically for interposer applications is furnished in a round, square, or rectangular format. Typical of the silicon-based interposer, the metal deposition process for a glass-based interposer enables very close coupling between related chiplet die elements mounted to its surface. Interconnection from the component side to the next-level terminal pattern on the opposite side is completed using through-glass via (TGV) processing. Via-hole forming may employ one or a combination of technologies: laser ablation (CO2, Excimer, UV), electrostatic discharge, mechanical drilling, chemical etching, or micro sandblasting. Via-hole features on the glass-based interposer may have via-hole spacing ranging between 50 to 100 microns, while the terminal land pattern features on the bottom surface of the interposer are commonly “fanned-out” to a wider 200- to 300-micron pitch. 

With most interconnects furnished on the interposer surface, the interface between the component(s) and package substrate can be significantly less complex. This, in turn, allows the contact pitch on the package substrate to increase and simplify the design of the host PCB:

• More efficient circuit routing 
• Minimizing circuit layer count 
• Improving power and ground distribution

Several methods have been developed for metallizing glass including copper alloy deposition, deposited silver paste, and printing with silver and copper inks.

Guidelines for designing the interposer may vary somewhat from one supplier to another, but the designer can use the data in Table 1 as a baseline to be confirmed or altered when discussing interposer fabrication with the designated supplier.

Keep in mind, semiconductor packaging methodology will continue to evolve and market analysts project a fairly steady growth in semiconductor package applications, requiring both interposer and high-density package substrate design capability in close proximity to the semiconductor fabrication source.

Note: The design guidelines furnished in Table 1 relate to copper alloy via filling and conductor formation. The geometries furnished in these tables were developed from my research and consensus among several colleagues involved in the technology. The data shown may not reflect the capability of all suppliers in their respective categories, but supplier companies will generally furnish the designer with alternative design guidance related to their material sets and specific process capabilities.

In part 3 of the Heterogeneous Interposer Design Challenge series, alternative chiplet terminal design, pattern variations, and advanced ultra-high-density hybrid joining methodologies will be explored.

Appearances

Vern Solberg will be conducting a half-day tutorial on “PCB Design Engineers’ Introduction to High Density Semiconductor Package Technologies,” March 19 at APEX EXPO, in Anaheim, California, where he will address “2D, 2.5D and 3D System-in-Packaging and Ultra High-Density Hybrid Bond Interconnect.”

Vern Solberg is an independent technical consultant, specializing in SMT and microelectronics design and manufacturing technology. He is the author of Design Guidelines for Surface Mount and Microelectronic Technology.