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Embedding Components, Part 6: Preparation for Active Semiconductor Elements

Designers are well aware that a shorter circuit path between the individual die elements, the greater the signal transmission speed, which significantly reduces inductance. By embedding the semiconductors on an inner layer directly in line with related semiconductor packages mounted on the outer surface, the conductor interface distance between die elements will be minimized.

Terminal Interface

The semiconductor fabrication process typically furnishes the die with an aluminum bond pad for the traditional gold-bond interface process. When alternative interface methods are required, the semiconductor terminals must be furnished with metalization that will be compatible with the attachment material or interface method. Companies using solder or conductive polymer for attaching the die element in the facedown orientation, for example, will need to employ techniques that enable liquidus material deposition, a solder reflow process, or a method for thermal curing followed by the dispensing of underfill polymer to negate air from between the die and laminate surface. The underfill material will require further thermal and vacuum processes to evacuate any trapped air and complete curing procedure.

Bond Pattern Redistribution

To enable efficient circuit routing, the semiconductor elements (while they remain in the wafer-level format) will likely be subject to additional metalization processes to redistribute the closely spaced wire-bond sites on the die perimeter to a more uniform array pattern within the central area of the die. In preparation for adding the redistribution layer (RDL), the fabricator will first sputter-coat a metal alloy adhesion layer onto the wafers active surface. Adhesion-promoting metals include nickel (Ni), molybdenum (Mo), chrome (Cr), tungsten (W), and titanium (Ti). Resist is applied over the wafer’s surface and photo-imaged to delineate the interconnect pattern and component termination sites (land patterns). The wafer(s) is then made ready for the electroplating process, building up additional metal over the exposed RDL pattern. Copper has become the preferred alloy for RDL circuit plating.

Following pattern plating, the resist coating is removed, and the remaining thin adhesion layer metalization is chemically etched from the silicon surface, leaving only the interconnect pattern and terminal lands. After cleaning, a photo-imaged passivation layer is applied to define the termination pattern and insulate and protect the conductive circuit pattern.

To read this entire column, which appeared in the December 2018 issue of Design007 Magazine, click here.