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Designers Notebook: Basic PCB Planning Criteria—Establishing Design Constraints

Printed circuit board development flows more smoothly when all critical issues are predefined and understood from the start. As a basic planning strategy, the designer must first consider the product performance criteria, then determine the specific industry standards or specifications that the product must meet. Planning also includes a review of all significant issues that may affect the product’s manufacture, performance, reliability, overall quality, and safety. Planning strategies must be established that will address several key issues related to the overall end-product manufacturing process:

• Design for manufacturing (DFM)
• Design for assembly (DFA)
• Design for test (DFT)
• Design for performance (DFP)
• Design for reliability (DFR)
• Design for safety (DFS)

Virtually all choices made during the PCB design planning process will affect every aspect of the final product’s cost, performance, and reliability, and its influence on the environment. The planning and development of the product becomes the joint responsibility of a team of individuals representing each technical discipline, and the circuit board designer is the key participant within this team. 

Component Selection and Placement
While most component parts are designed for surface mounting, some devices (connectors, power components, and the like) may require through-hole mounting. Component standards have also become vital in the evolution of product miniaturization, reinforcing the manufacturing infrastructure and developing guidelines for most commercial semiconductor package outlines.

Semiconductor package outline standards are developed and documented by industry members of the U.S.-based Joint Electron Device Engineering Council (JEDEC) and the Japan Electronics and Information Technology Industries Association (JEITA). In regard to product quality, workmanship assessment, and reliability testing standards, manufacturers (both domestic and international) rely on standards developed by industry members of the International Electrotechnical Commission (IEC) and the Global Electronics Association (formerly IPC). These standards have been developed to help manufacturers achieve quality, reliability, and consistency of their end products.

Although the interconnect of less complex circuit boards can be accommodated on the outer layers of the circuit board, the transfer of most of the interconnects between components on the higher component density applications will require subsurface circuit layers; a minimum clearance area around each device must consider access for inspection, and when necessary, rework or replacement of defective components:

• Maintain uniform spacing between passive components
• Establish minimum clearance for semiconductor packages
• Avoid close spacing to and between higher profile devices
• Determine clearances for rework tool access
• Consider specialized equipment for removal and reattachment of large ICs

When planning component placement and estimating the area requirement, consider both component outline dimensions, overall component thickness or height, and, to enable automated assembly and post-process inspection, the minimum clearance recommended (Figure 1) between components. 

Establishing PCB Assembly Process and Design Complexity
The circuit board complexity can range from the very basic one- or two-layer substrate to the more complex multilayer construction. As component density increases, several key issues must be addressed:

• Ratio of surface mount passive to active component area 
• Physical variations of pin-through-hole (PTH) components
• Power and ground distribution and thermal management
• Allowable number of circuit layers
• One side or two side, mixed (SMT and PTH) technology

To avoid potential delay in the overall manufacturing process, the PCB design engineer will need to have a clear understanding of the designated PCB supplier’s process capability and design rule criteria. If possible, establish a communication channel with the PCB supplier to review and evaluate the circuit board design file before prototype fabrication and again before releasing the design for production quantity.

To assure a successful outcome of circuit board fabrication, it is important that the designer recognize the manufacturing process complexities and associated cost impact, especially when implementing the more sophisticated fabrication procedures. 

Conductor routing protocols must be established in advance—the space separating via-hole lands, microvia lands, and/or component attachment lands (referred to as “channel width”). When these channels are restricted, the designer will need to consider reducing conductor line and space widths or resort to sub-surface circuit routing to achieve interconnect goals. Although necessary for the more complex applications, multilayer circuit board fabrication will add to both fabrication complexity and increased cost.

PCB fabricator specialist suggests that the circuit board design engineer consider some of the major factors impacting unit cost:

• Layer count (2, 4, 6, 8…)
• Laminate type (material)*
• Overall size of the PCB
• Base copper weights in different layers
• Lines and spaces on different layers
• Pad sizes and PTH-to-Cu clearance
• Aspect ratio and number of holes 
• Surface finish

*Laminate materials, although having similar attributes, may be priced differently, depending on the supplier location and the number of layers. 

Base material specified and manufacturing technology required will effectively determine overall PCB fabrication cost. As a reference, Table 1 represents a typical PCB pricing scheme using a two-circuit layer PCB as a base price factor.

Table 1: Production pricing guide for an 18" x 24" panel (Materials represent approximately 20% of the total bare board cost)

With regard to PCB size, it is common practice to arrange smaller outline PCBs onto a larger outline panel arranged in an array format. This will increase process efficiency but the unit cost impact will ultimately be based on the overall panel yield (reduced by the number of individual boards on the panel that are unacceptable). 

As the density factor compresses, the area surrounding each component is reduced. To resolve connectivity issues, the designer will need to consider implementing narrower widths and spacing for conductor routing. Before reducing topography features, however, review the designated circuit board supplier’s “standard capability” and the potential cost impact when implementing higher density (HDI) fabrication technologies, such as sequential buildup construction with smaller vias, blind and buried vias. The process related factors that will impact finished PCB cost are furnished in Table 2.

PCB design rules can be classified into different technology levels: high-, medium-, and low-tech. Each level applies to a specific supplier’s capability and each will follow standard or advanced rules. Before committing to adopting HDI or UHDI technology, the designer should confirm that the PCB supplier(s) selected can furnish the preferred complexity level at the anticipated production quantity.

• Review your PCB supplier’s material offerings
• Discuss any unique base material or copper foil needs
• Clarify layer stacking alternatives with supplier
• Define power and ground distribution objectives
• Specify controlled impedance requirements

When estimating circuit boards’ manufacturing cost, the designer must consider materials, circuit density, the number of circuit layers, and fabrication process complexity. While mechanically drilled and plated via-holes are a mature technology for multilayer circuit board fabrication, the buried via and laser-ablated blind microvia-hole forming require more sophisticated systems. 

Circuit Interconnect Planning
Before beginning the PCB design, the designer must establish the key operating conditions of the end product. For example, understand the relationship between the thickness of the copper foil and the finished conductor width that will be necessary to comply with the expected current-carrying requirement. The operating temperature of the product can also affect the efficiency of the copper conductor’s current-carrying capability. 

The dielectric base material is supplied with copper foil pre-laminated onto one or both sides, but copper foil materials can be specified in sheet form for sequential lamination with a variety of optional surface topographies. The general-use foil has a rather rough surface on one side, ensuring a reliable bond between the copper and resin layer of the laminate material. 

External layer copper foils, for example, will begin with a thickness equal to the foil thickness on internal layers. During the electroplating process, an additional copper thickness is formed onto the base-copper foil surface. Base copper foil thickness variations and the minimum post-plating process conductor thickness for IPC Class 1, 2, and 3 circuit boards are defined in Table 3.

Table 3: Estimating current-carrying capacity of copper foils

Another factor that affects the current-carrying capability is location of the circuit. The circuit conductors on the outer layer(s) of the circuit board and those laminated within the subsurface layers will have differing proficiencies. For example, the current-carrying capacity of the external layer conductor may require 2X the thickness of that defined for the internal layer conductor. 

Note: For greater detail in determining the current-carrying capacity for printed circuit conductors, refer to IPC-2152. This document sets the industry standard for defining the appropriate sizes for both internal and external conductors as a function of the current-carrying capacity required as well as calculating the finished copper conductor’s temperature rise potential.

Predetermine Power and Ground Distribution
For the less complex single- and two-sided circuit structures, power and ground can be integrated within signal interconnects. The conductors assigned to distribute power and ground will typically be the first stage of the interconnect planning process, furnishing a significantly wider conductor than the signal-carrying conductors. When the power and ground are retained on dedicated circuit layers, they will contribute to improving signal integrity by suppressing electromagnetic (EMI) noise and interference.

Power and ground can be distinct areas of copper foil or the entire surface of internal layers of the circuit board. How this is achieved will depend on the type of circuit board design system employed. Most CAD systems furnish the ability to define a power and ground area that appears as a solid graphic representation. When an area of copper is retained on the outer surface of the circuit board, it will likely be positioned to service ground isolation of specific components or a group of related components. For mixed function applications, the designer may divide the power and ground planes on an inner circuit layer to isolate differing voltage and ground potentials. 

Preparing for Surface Mount Assembly
Surface mount assembly is a highly controlled method for producing electronic circuits using a broad range of miniature passive and active components mounted or placed directly onto the surface of printed circuit boards. The component outlines and terminal configurations can be very different, relying on perfectly matched land pattern geometries to ensure a reliable electrical interface between component and circuit board. The flow diagram illustrated in Figure 2 furnishes thebasic “print-place-solder reflow” process sequence for a single-side surface mount assembly.

Surface mount assembly processing relies on specialized systems and strict process controls. The surface mount component type selected (passive and active, coarse-pitch, fine-pitch, BGA, CSP) will determine the assembly methodologies required. 

Solder materials developed for surface mount applications are primarily a tin alloy-based powder and flux composite. The solder paste material is commonly deposited onto the component land patterns using a contact stencil printing process that distributes a precise volume of solder onto the components’ land patterns. Although not practical for many high-volume SMT assembly applications, dispensing solder paste has proved ideal for prototype or low-volume applications, components with very exacting solder volume requirements, or where solder is to be deposited into narrow recesses not accessible using stencil printing.

Note: The assembly specialist should be consulted before specifying PCB surface plating or coating material.

The following plating and coating alternatives provide a flat, uniform, low-profile, solder process-compatible surface finish: 

• IT and IS: Immersion tin and immersion silver
• ENIG: Electroless nickel/immersion gold
• ENEPIG: Electroless nickel/electroless palladium/immersion gold 
• OSP: Organic solderability preservative

Developing the HDI or UHDI circuit board is not a trivial endeavor. Materials and process complexities play a significant role in terms of manufacturability and the direct cost of fabricating multilayer circuit boards. The challenge here is to select the most suitable base materials for the application while meeting the end-product’s electrical and operating environment requirements.

The best advice for the circuit board designer is to establish a dialogue with the circuit board fabrication specialist early on for each new design. In regard to fabrication process efficiency and meeting the cost target for the circuit board, fabricators encourage the designer to evaluate the overall physical aspects of the circuit in order to simplify the design.

For example, reducing conductor width and spacing will significantly contribute to reducing layer count. As far as implementing SBU technology, the most expensive stackup configuration requires multiple sequential laminations. So, reducing the circuit layer stackup on each side of the board will have a very positive impact on unit cost.

Resources

• Rush Inc., a U.S.-based PCB manufacturing service company based in Silicon Valley
• Design Guidelines for Surface Mount and Microelectronics, by Vern Solberg

This column originally appeared in the July 2025 issue of Design007 Magazine.