Estimated reading time: 7 minutes

Happy’s Tech Talk #47: Automation for Complex Multilayer Fabrication Stackups

Multilayer stackups have evolved dramatically as they’ve been adopted for high-performance computing (HPC) and artificial intelligence (AI) server applications. These high-speed, high I/O designs require the designer and fabricator to manage more boundary conditions than ever before. In practice, the stackup is no longer “just a stackup.” It becomes the foundation for signal integrity, reliability, manufacturability, and cost.

For today’s HPC and AI servers, the following considerations typically drive success or failure:

• Importance of materials and stackup in high-speed design
• Interaction of mechanical and electrical parameters
• Materials and via planning
• Best practices in stackup design
• Simplified multilayer fabrication approaches
• Sequential lamination, vias, materials, and plating
• Lamination process cycles and registration
• Impedance planning and signal integrity
• Relevant specifications, standards, and test methods

In Figure 1, implementation and validation can easily become a 10-step process when you include fine-pitch packaging (driving HDI) and vast BGA arrays (driving layer count). It has become a workflow requiring modeling, validation, and increasingly, automation.

Basic Stackups/Best Practices in Stackup Design
For a complex multilayer, selecting the materials matters as much as choosing the construction type and via structure. Modeling and simulation help reduce cost and risk by defining the number of layers, design rules, impedance targets, and reliability expectations before fabrications begins.

Most of this information results from understanding laminate datasheets and using stackup planners like the Z-Zero and Polar resources.¹ Material systems must be compatible with HDI via structures, especially in sequential lamination builds.²

Once the material system and thickness ranges are understood, the designer can select the right dielectric thicknesses for frequency planning and impedance design. A good example of this approach is illustrated in papers by Gerry Partida of Summit Interconnect.^3,4

Gerry’s simulations (for example, Avishtech’s Gauss Stack and Gause 2D³) show that sequential lamination and stacked microvias are reliable when the proper material systems are selected and used correctly. This completes the design phase for implementation but now, as illustrated in Figure 2, the process must continue into validation with the fabricator.

Material characteristics (Figure 3), documented in books published by I-Connect007, provide insight into selecting the proper material system and understanding trade-offs.

Validation with the fabricator (Figure 1, steps 6–10) provides the feedback loop confirming that the multilayer stackup will perform, meet impedance requirements, and be reliable over time. Additional DFM checks and signal integrity/impedance modeling help complete the validation phase.

Hardware-Tooling and Equipment
In complex multilayer fabrication, other critical processes include tooling, multilayer presses, and via filling.

ML-PWB Tooling

The current best practice is pinless lamination stackup. New automated equipment is now available from several vendors to support this approach.

Pin tooling plates have been used for lamination since the early 1960s. I first encountered multilayer stackup when I was assigned to increase capacity for our multilayer output in 1972. In those days, we used mechanical pins and tooling holes to align layers. It worked, but it introduced its own tolerance stackups, and anyone who has fought multilayer registration knows exactly what that means.

Pinless systems, using optical alignment and inner-laying welding, offer a major improvement in both registration accuracy and process predictability.

Automated Optical Alignment and Pinless Layup Process
The optical alignment process is like manual layup, but faster and more accurate, with automated checks to ensure correct material order and orientation. A typical process includes:

1. Place the lower lamination plate on the layup table and begin layup as usual up to the first separator plate.
2. After placing the first separator plate, place the untooled copper foil (this foil will be outside layer n).
3. Place the untooled prepreg (all prepreg between layers n–2 and n–1).
4. Align prepreg using two perpendicular laser layup lines (Figure 4).
5. Continue placing material up to layer (core) 1 and 2, then activate the welding head.
6. Place the welded package along the two perpendicular laser lines. The welded package consists of layers 2 to n–1 with prepreg welded in place between the layers.
7. Place untooled prepreg (between layers 1 and 2).
8. Place the untooled copper foil (this will be layer 1).
9. Place the next separator plate and repeat for the entire book.

The inner layers must first be prepared with the corresponding fiducial targets on the top and bottom sides for optical alignment (Figure 4). The prepreg does not require holes or punching. The inner layers must include weld coupons etched in the reserve zones (Figure 5). These coupons can be placed along the panel edges or inside the image area, if necessary.

The use of fiducial targets aligned through CCD cameras and image processing becomes the critical alignment step. This reduces manufacturing and maintenance by eliminating the cost of pins, bushings, and tool separator plates from the lamination process.

The weld coupons replace the old drilled or punched registration holes. Coupon designs vary, but typical sizes range from 6–10 mm wide by 15–40 mm long, with copper clearances as recommended by the equipment supplier. All include solid copper decals (Figure 6). Each supplier provides additional process details based on years of field experience.

Multilayer Presses and Process Cycles
The welded coupon bonding process is like the induction lamination process (Figure 6). The welded book can better withstand the dilations and shrinkages of the hot-press cycles, allowing the best possible linear movement of all layers during lamination. It reduces internal stresses that cause warping and deformations, and moreover, reduces distortions and misalignments between inner layers.

Another practical benefit is that welded multilayer stackups can be X-rayed to check before and after lamination to verify registration and help adjust compensation factors.

Advantages of Pinless Lamination
Pinless lamination offers several advantages:

• Increased layer-to-layer registration accuracy
• Increased process predictability and improved registration data
• Improved ability to characterize lamination press processes
• Better registration of thin cores (accurate and consistent)
• Flexibility using lamination plates without tooling holes
• Fewer lamination plates required (usable across multiple panel sizes)
• Separator plates without tooling holes (fewer sets required)
• Cleaner operation (no resin-filled tooling holes to clean)
• Prepreg does not require pin clearances (minimizes prepreg dust)
• More flexibility in panel sizes without pin restrictions
• Elimination of pins and bushings (remove consumables)
• No depinning required

Impedance Planning and Signal Integrity
The advances in semiconductor fabrication over the past 50 years have been dramatic. When I started college, integrated circuits had only a handful of transistors. Today, many devices contain billions. That’s revolutionary, but it also means transistors switch extremely fast.

As a result, many PCB interconnects must be treated as transmission lines even when the system clock appears relatively slow. For multilayers, impedance planning and signal integrity are essential.

Verification of the multilayer stackup with the fabricator is critical because the final pressed thicknesses will vary between fabricators and can differ from datasheet values. Field-solver selection is also important,  as well as these factors:

• Dielectric height and crosstalk control
• Dielectric and hybrid material selections
• Fiber-weave effect
• Stackup wizard accuracy and limitations
• Detailed understanding of plating impacts
• Stacked vs. staggered vias

Fortunately, there are many excellent resources to help educate designers on these issues.^{1, 2}

Summary
A data-driven strategy for the creation of a multilayer stackup is essential for performance and reliability in HPC and AI server designs. Signal integrity and power integrity challenges, combined with finer component pitches and higher connection counts, create a unique set of demands for today’s PCB designer.

The most successful programs treat stackup design as a complete workflow: modeling and simulation, material selection, validation with fabricators, and manufacturing processes that improve predictability. Automation, especially pinless layup and optical alignment with welding, can significantly improve registration and consistency in complex sequential-lamination multilayers.

References

1. More Secrets of High-Speed PCBs by Martyn Gaudion, Stackups: The Design within the Design by Bill Hargin, The HDI Handbook by Happy Holden, and many more.
2. Stackups: The Design within the Design by Bill Hargin, pg. 67, 2022.
3. “PCB Tech Match: How to Choose the Right PCB Technology for Your Application,” by Gerry Partida, Oct. 3, 2024.
4. “Next Progression in Microvia Reliability Validation—Reflow Simulation of a PCB Design Attributes and Material Structural Properties During the PCB Design Process,” by Gerry Partida, IPC APEX EXPO, 2022.

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers. 

This column originally appeared in the March 2026 issue of I-Connect007 Magazine.