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Happy’s Tech Talk #42: Applying Density Equations to UHDI Design

With the need for faster speeds, more parts on an assembly, and the trend to make things smaller for portability, the printed circuit design and layout process is both creative and challenging. The process involves “applying the density equation” while considering certain boundary conditions, such as electrical and thermal performance. Unfortunately, many designers don’t realize there is a mathematical process to laying out a printed circuit. The density equation below has two parts: the left side, which is the component wiring demand, and the right side, which is the substrate wiring capability.¹

Component Wiring Demand
Wiring demand is the total connection length required to connect all the parts in a circuit. When you specify an assembly size, you create the wiring density in inches per square inch or centimeters per square cm (Figure 1). Models early in the design planning process can estimate the wiring demand. Three factors can control the maximum wiring demand:

1. The wiring required to break out from a component like a flip chip or chip-scale package.
2. The wiring created by two or more components is tightly linked, like a CPU and cache, or a DSP and its I/O control.
3. The wiring demanded by all integrated circuits and discretes collectively.

There are models available to calculate the component wiring demand for all three cases. Since it is not always easy to know which case controls a design, I usually calculate all three cases to see which is the most demanding and thus controls the layout. The model I find most useful for Case 3 is Coors and Anderson’s statistical wiring requirement.²

Other widely used models are:

• Rent’s Rule Technique³
• Toshiba Technology Map⁴
• Donath Method⁵
• Section Crossing Method⁶
• Geometric Approach⁷

Each has circuit topology conditions that will differentiate which model to use. All these models are described in the HDI Handbook.

Getting Over the Density Wall

To achieve higher routing density, there are only five degrees of freedom:

• Smaller traces
• Traces closer together (spaces)
• Smaller vias (down to microvias)
• Smaller annular rings for the vias
• Higher layout efficiency when routing⁸

I am talking about routing density on a single layer; more signal layers will result in a greater total routing distance on a board.If you reduce some of the variables in Equation 1, the resulting routing density will increase. The largest effect on density is reducing the trace width, but this can come with electrical issues. The next best way to increase density is to reduce the via’s annular ring, but a very small AR will significantly reduce the via’s reliability.

Coors and Anderson’s Statistical Wiring Requirements

This wiring demand model is based on a stochastic model involving all terminals. The probable wire length is calculated based on the distance of a second terminal and the spatial geometry of all other terminals. This is the most recently determined wiring model and represents the most practical approximation of surface mounting technology. The equations below present the mathematical model (Figure 2).

Adjusting the Wiring Density Model
The best way to improve this model is to normalize it to your company’s design constraints by determining the sigma (d) of your most dense boards (this will be predicted) and taking the design and sum of the total wiring lengths on each signal layer (actual). A regression fit will show your wiring density, as seen in Figure 3.

Summary
Ultra HDI design is new to many designers. Optimize the appropriate design rules and layer stackup by first predicting what the circuit and components require. See the illustrated Coors Statistical Model, and you can use other references to models. This can be an insightful first step in applying UHDI.

References

1. The HDI Handbook, by Happy Holden.
2. “A Statistical Approach to Wiring Requirements,” by G. Coors, P. Anderson, and L. Seward. Proceedings of International Electronics Packaging Society (IEPS) 1990, pp. 774–783.
3. Principles of Electronic Packaging, by D.P. Serpahim, R.C. Lasky, and C.Y. Li., pp. 39–52.
4. “New Polymeric Multilayer and Packaging,” by H. Ohdaira, K. Yoshida, and K. Sassoka. Proceedings of Printed Circuit World Conference V, Glasgow, Scotland, reprinted in Circuit World, Vol. 17, No. 12, January 1991.
5. “Placement and Average Interconnection Lengths of Computer Logic,” by W. Donath. IEEE Transactions on Circuits and Systems, No. 4, 1979, pp. 272–277.
6. “How Big Should a Printed Circuit Board Be?” by S. Sutherland, and D. Oestreicher. IEEE Transactions on Computers, Vol. C-22, No. 5, May 1973, pp. 537–542.
7. “Electronic System Packaging: The Search for Manufacturing the Optimum in a Sea of Constraints,” by L. Moresco, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 13, 1990, pp. 494–508.
8. “Predicting HDI Design Density,” by Happy Holden, and R. Charbonneau. The Board Authority, Vol. 2, No.1, April 2000.
9. “Happy Thoughts: Calculating Your Fabrication Capability Coefficients,” by Happy Holden, CircuiTree, Feb. 2006.

Happy Holden has worked in printed circuit technology since 1970 with Hewlett-Packard, NanYa Westwood, Merix, Foxconn, and Gentex. He is currently a contributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engineers.

This column originally appeared in the August 2025 issue of Design007 Magazine.