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Beyond Design: Practical Signal Integrity

"There are two types of designers: Those that have signal integrity problemsand those that will." — Sun Microsystems.

If you are a digital designer, you will eventually have SI problems whether you like it or not. But all is not lost. If you learn to work with these issues, then you will soon become proficient with high-speed design.

Advances in semiconductor lithography enable IC manufacturers to ship smaller and smaller dies. However, Moore's law (1965) is still in effect: The number of transistors on ICs doubles every two years and will continue for at least 10 years. Arguably, the predictions about the law were short-sighted, and the paradigm will continue to apply as chip sizes continue to scale down. But keeping up with it is becoming more challenging. Intel for instance, changed transistor structure into 3D form, by placing transistors on top of each other, on the latest 22 nm process to enable them to continue shrinking silicon.

Each new generation of semiconductor process technology delivers greater levels of integration, higher performance and lower cost. However, these benefits are offset by increases in power consumption that seem to unavoidably accompany each reduction in feature size. In order to reduce power consumption, IC manufacturers have moved to lower core voltages and higher operating frequencies which of course mean high current requirements and faster edge rates.

Faster edge rates mean reflections and signal quality problems. So even when the package and your clock speed haven’t changed, a problem may exist for legacy designs. The enhancements in driver edge rates have a significant impact on signal quality, crosstalk, timing and EMI. So whether you like it or not,welcome to the domain of high-speed design.Read the full column here.Editor's Note: This column originally appeared in the August 2013 issue of The PCB Design Magazine.