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Beyond Design: Pre-Layout Simulation

Pre-layout simulation results for an address line shown in Figure 6 include the effect of a 22-ohm series terminator near the driver, and a 200-ohm pull-up at the end of the line to VTT (0.9V). The VTT pull-up is typically between 100 – 200 ohm and is determined by simulation.

Figure 6. Pre-layout address simulation results (MA0).

Establishing Routing Rules

Before starting placement and routing, detailed interconnect-routing constraints should be established. These are of course based on the pre-layout simulation. The matched length data, address, strobe/clocks, command and control signals should be setup in the constraints editor, along with differential pair rules, clearance between signal groups (to prevent crosstalk) giving priority to critical signals. Furthermore, return paths should be checked to ensure that there are no split planes or obstacles to delay the return current. Further details of the tolerances required are highlighted in my previous article “PCB Design Techniques for DDR, DDR2 & DDR3.”

Figure 7 shows the data lane routing for a DDR2 design. The trick is to closely match the data signals, data masks and associated strobe (which act as the data clocks). Results of pre-layout simulation of the data signals in Figure 4 show very close correlation with post-route simulation of the same signals in Figure 8.

Figure 7. Data and strobe lines for each data lane.     

Figure 8. Note close timing between the data signals (MDQ0) and the data strobe (MDQS0) for a DDR2 interface.

Figure 9 shows the results of the routing process. However, before doing this, the daisy chain topology was simulated to establish whether the VTT end-of-line pull-up is required, and if a series terminator is also necessary.

Figure 9. Routing results. 

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