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Signal Integrity, Part 1 of 3

As system performance increases, the PCB designer’s challenges become more complex. The impact of lower core voltages, high frequencies, and faster edge rates has forced us into the high-speed digital domain. But in reality, these issues can be overcome by experience and good design techniques. If you don’t currently have the experience, then listen-up. This three-part series on signal integrity will cover the following topics:

1. How advanced IC fabrication techniques have created havoc with signal quality and radiated emissions.
2. The effects of crosstalk, timing and skew on signal integrity.
3. Where most designers go wrong with signal integrity and how to avoid the common pitfalls.

Technology is moving fast and much has changed over the past 25 years that I have been involved in high-speed multilayer PCB design. Particularly, advances in lithography enable IC manufacturers to ship smaller and smaller dies on chips. In 1987, we thought that 0.5 micron technology was the ultimate, but today 22 nm technology is common.

Also, power consumption in FPGAs has become a primary factor for FPGA selection. Whether the concern is absolute power consumption, usable performance, battery life, thermal challenges, or reliability, power consumption is at the center of it all. To reduce power consumption, IC manufacturers have moved to lower core voltages and higher operating frequencies, which of course mean faster edge rates. However, faster edge rates mean reflections and signal quality problems. So even when the package has not changed and your clock speed has not changed, a problem may exist for legacy designs. The enhancements in driver edge rates have a significant impact on signal quality, timing, crosstalk, and EMC.

Read the full column here.


Editor's Note: This column originally appeared in the October 2014 issue of The PCB Design Magazine.