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Designers Notebook: Implementing Strategic Planning Principles for PCB Design

Developing multiple-processor system-level products involves a broad range of engineering disciplines (commonly referred to as co-design), often led by a designated program manager who divides the development program into technical disciplines.

The primary member of this team is the electrical engineer (EE), who prepares the overall schematic diagram of the product. This effort includes simulation and modeling, developing a BOM, and defining all active components and any specialized passive elements (often stipulating preferred or prequalified sources).

When developing a product for use in a specific environment, such as harsh operating conditions, avionics, or automotive, for example, an engineer specializing in product certification, electrical test, and physical stress testing may be assigned to confirm that the end product will meet all designated standards or special requirements defined by the end user. The mechanical design engineer assigned to the program will then furnish the PCB design engineer with the overall physical specification for the circuit board, physical outline, the base materials best suited for the application, laminate type and source, and finished plating and coatings (solder mask), as well as establishing the finished board’s maximum thickness.

The key member of this team, after all, is the PCB design engineer, who is responsible for converting the schematic representation of the product into a tangible, physically functioning PCB ready for assembly.

Establishing PCB Design Strategy
Before beginning the design process, the PCB designer will perform an interconnect capacity analysis to establish the basic component area requirement. In preparation, the PCB design engineer must first gather mechanical outline specifications and electrical data for all active and passive component parts. From this data, the designer assigns the associated land pattern geometries and pad stack data from the pre-established CAD library. For those components without existing descriptions and pad-stack data, the manufacturer’s mechanical and electrical information must be documented to enable creation of the new part(s).

To calculate the basic area required for component placement and circuit interconnect, designers must contemplate the land pattern features for mounting the components, define keep-out zones, and establish clearances reserved for the assembly process and post-assembly evaluation, as well as the allowances needed for rework and repair. The final analysis will provide the designer with an estimated maximum surface area needed to complete all circuit interconnects.

Conductor routing protocols must be established in advance. The space separating via-hole lands, microvia lands, and/or component attachment lands is referred to as “channel width.” The channel widths for routing array-configured (BGA, FBGA, WLBGA) semiconductors are calculated using the terminal pitch (center-to-center distance) and the land pattern size. This defines the maximum number of conductors that can be routed between each channel (conductors per channel), as demonstrated in Figure 1.

The factors that define the limits of circuit conductor routing ability in a substrate are:

• Pitch (distance) between land patterns and via-hole lands in the substrate
• Number of conductors that can be routed between those features
• Maximum number of sub-surface signal layers required

The spacing between circuit conductors must account for the established minimum electrical clearance for fabrication process variables, solder mask surface adhesion, land pattern features, via-hole lands, and other fixed elements on the board.

PCB Circuit Density Analysis
When defining the board’s complexity level, the designer will first establish a criterion for fabrication, including the board outline and thickness limitations. Regarding the specified circuit board thickness limit, clear objectives must be established to determine how many circuit layers are dedicated to signal routing and how many are reserved for power and ground distribution. This helps determine the component density and interconnect complexity.

While a significant number of semiconductor packages will have a moderate level of complexity (I/O and terminal pitch), others may have an excessively high I/O density. One solution to conductor routing roadblocks is to adopt blind via-in-land techniques to assign a majority of the interconnect to the sub-surface layers. When component density restricts circuit routing on the outer surface, subsurface circuit routing can be justified. Adapting blind and buried microvia holes as well as predefined conductor routing channels will help the designer facilitate efficient interconnection of these often very fine-pitch and high I/O array terminal configured semiconductor packages.

The complexity of fabricating the circuit board must always be a consideration in cost control so a limit may be preestablished to restrict the number of circuit layers.

Figure 2: Sequential 3-4-3 build-up circuit board cross-section view: a) Vertically stacked, laser-formed, Cu-filled microvias joining build-up layers; b) Buried, mechanically drilled, and plated via in four-layer core section; c) Stagger-stacked, laser-formed microvias to join build-up layers; d) Blind and plated laser-formed and Cu-filled layer-to-layer microvia; e) Mechanically drilled and plated through-hole. (Source: KSG Europe)

Sequential Build-up (SBU) PCB Processing
SBU offers a variety of design options. Designers can choose sequential build-up using stacked microvias for layer-to-layer interconnect or the staggered microvia, where via-holes are offset from one layer to another. The SBU board’s complexity is ultimately determined by component density, circuit interconnect density, and the number of signal conductor layers plus the number of layers dedicated to power and ground.

The sequence in which the circuit board layers are assembled (signal, power, ground, etc.) is a key factor affecting signal transmission performance. Layer count and the method selected for interconnect between circuit layers, for example, will have a significant influence on controlling process complexity. Implementing blind microvia technology for layer-to-layer interconnect can enable significantly greater circuit routing density, but the build-up process substantially increases the manufacturing complexity since it will affect the number of lamination cycles.

Some of the more complex SBU designs, for example, may require 15 or more lamination cycles. With each lamination cycle, the core materials are subjected to repeated exposure to elevated temperatures and high pressure. The concern is that excessive lamination cycles can contribute to material decomposition, especially a concern for the very thin, multiple layer circuit boards commonly developed for hand-held or portable communication products. These PCBs, in particular, will be more prone to board warping during assembly.

Planning PCB Fabrication
Although rarely an employee of the actual product development company, a key member of the engineering co-design team is the circuit board fabricator, which commonly furnishes practical guidance that helps ensure efficient fabrication processes, maximize yield, minimize cost, and reduce complications.

“One of the more common mistakes designers make in creating multilayer structures is that they are often unnecessarily complex.”

A prominent PCB manufacturer in Silicon Valley made the following observations:

1. Space constraints, due to the increasing number of signal conductors, increased component density, and number of terminals, will limit the open area on the PCB’s surface. This factor can impede the designer’s effort to provide the most efficient interconnect circuit routing. Circuit routing becomes increasingly challenging as the spacing between terminal lands decreases.
2. As the component density increases and board surface area becomes restricted, it will force the designer to rely on additional circuit layers for subsurface circuit routing. An excessive increase in circuit layers, however, will impact both fabrication efficiency and manufacturing cost.

Challenges facing the fabricator include:

• Tolerance control when aligning all layers in the stackup
• Maintaining layer-to-layer registration during lamination
• Consistent thickness control of the finished board
• Avoiding hole breakout of mechanically drilled holes

Fabricators should caution designers to exercise restraint in layer count and in implementing overly complex layer-to-layer interconnect schemes. The cost impact attributed to process complexity can adversely affect the competitive position of the end product. Yes, refinement of the board design will require more effort and a little more time, but simplifying the design at this stage of development can reduce fabrication complexity, processing time, and cost.

Note: I have learned that establishing a business relationship with the fabricator early in the development cycle will contribute to both end product reliability and performance. They can assist in selecting the most suitable materials and fabrication method for the application, i.e., subtractive vs. semi-additive circuit definition, conventional multilayer vs. sequential buildup, mechanical drilling vs. laser microvia processing (stacked or staggered). Their goal is to give you a reliable, high-yield product at an acceptable cost.

This column originally appeared in the August 2026 issue of I-Connect007 Magazine.