Fresh PCB Concepts: Designing PCBs for Harsh Environments—Reliability Is Engineered Upstream
Elementary, Mr. Watson DFX—Basically a Basket of Crabs With Spreadsheets
Target Condition: When Design Outpaces Manufacturing
Beyond IPC-2152: Creating Technology-specific Current-carrying Capacity Design Charts Using Thermal Modeling
January 29, 2026 | Mike Jouppi, Thermal Management LLCEstimated reading time: 1 minute
Designers commonly size traces using online calculators based on IPC-2221 or IPC-2152 charts, selecting width and thickness for a given current and allowable temperature rise (ΔT). Consideration is given to parallel conductors, although this is not a practical evaluation method for most designs. An important aspect of trace heating, especially groups of traces, is the power dissipated by the conductors. Unfortunately, the power dissipation or a method for accounting for power losses in the traces/conductors or planes is not straightforward.
The thermal design of a PCB must consider all components, their power requirements, board material, board stackup, mounting conditions, environmental conditions, and trace/conductor power losses. PCB thermal analysis considers both steady state and transient conditions. We will discuss steady-state trace heating.
It's a common practice to determine a trace size based on current, steady-state temperature rise, and trace cross-sectional area. The issue is that the IPC chart temperature rise is much higher than what would be found for most designs. Additionally, trace power is not initially assessed, leaving a significant amount of power, especially in high-current designs, to be managed later in the design cycle.
Consider a previous PCB design used to create design charts for that PCB technology. A process for creating technology-specific design charts (TSDC) can be used to develop conductor sizing design charts that account for all PCB thermal design parameters. This provides a lot of new insights into your board technology. This process for generating PCB-specific current-capacity charts is documented in U.S. Provisional Patent 63/875,465.
It’s possible to evaluate the varying current-carrying capability around different areas of the board that have more or less copper. Design charts can be made for many different environmental conditions, such as on a lab bench or for worst-case operating conditions. A previous design is not necessary; it simply minimizes iterations and provides the designer with a lot more useful information.
To continue reading this article, which originally appeared in the January 2026 I-Connect007 Magazine, click here.
Share on:
Testimonial
"Our marketing partnership with I-Connect007 is already delivering. Just a day after our press release went live, we received a direct inquiry about our updated products!"
Rachael Temple - AlltematedSuggested Items
PCB Technologies to Exhibit at PCB East 2026
04/23/2026 | PCB Technologies Ltd.Issey Ende, PCB-Technolgies’ VP of Sales and Marketinghas announced that his company will be exhibiting at this year’s PCB East 2026, the premier East Coast conference and exhibition for the electronics design, fabrication, and assembly industry on Wednesday, April 29, 2026, at the DCU Convention Center in Worcester, Massachusetts.
Design for Test: A New Book from The Test Connection, Inc.
04/23/2026 | Real Time with... APEX EXPOBert Horner, president of The Test Connection Inc., shares insights on designing for testability (DFT) challenges with Kelly Dack. Horner discusses the critical need for incorporating testability early in the design process and the importance of quantifiable metrics for measuring test coverage. He highlights The Test Connection's role in transferring decades of 'tribal knowledge' to emerging engineers through training and education. Look for "The Printed Circuit Assembler's Guide to... Design for Test, A Practical Guide to Test and Inspection" in the I-007eBooks library.
Changing Times: Siemens Plans to Sell Former Mentor Graphics Wilsonville Campus
04/22/2026 | Nolan Johnson, I-Connect007Siemens announced it will be selling its Wilsonville, Oregon, property, which has served as the campus for Mentor Graphics, which was later acquired by German EDA-giant Siemens, as reported by The Oregonian on April 20. Siemens will maintain one building on the sprawling 53-acre campus, citing the move to hybrid and remote work over the past few years as a key factor in the decision.
Siemens Collaborates with TSMC to Advance AI for Semiconductor Design
04/22/2026 | SiemensSiemens announced the continuation of collaboration with TSMC to drive innovation in AI-powered automation and advanced semiconductor design enablement.
Standardization, Workforce, and the Road Ahead for Flex–Packaging Integration, Part 3
04/22/2026 | Anaya Vardya, American Standard CircuitsParts 1 and 2 of this series established the technical foundation and application landscape for the convergence of flexible PCBs and advanced semiconductor packaging. Part 3 addresses what comes next: the standards frameworks, talent pipelines, and strategic imperatives that will determine whether the industry can scale this convergence reliably and competitively.