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Beyond Design: The Impact of Signal Rise Time on Bandwidth

The term bandwidth was first used years ago in the RF world to represent the range of frequencies in a signal. In digital electronics, we also use the term to describe the signal spectrum since square waves are made up of numerous sine waves (harmonics) of the fundamental frequency (Figure 1). For digital signals, the lowest frequency is always the DC component (zeroth frequency) and the highest frequency component is the maximum frequency that is significant (typically the fifth harmonic). The shorter the rise time in the time domain, the higher the bandwidth in the frequency domain, and the more closely the waveform resembles an ideal square wave. In this month’s column, I will look at the relationship between signal rise time and the bandwidth of a digital signal.

Rise time describes how quickly a digital signal can change from a low state to a high state. A signal must have a fast enough rise time to accommodate the data being processed. Otherwise, information in the waveform (circuit timing) may be lost. However, a signal does not have to have a faster rise time than is required by the system. Faster is not necessarily better as it may create ground bounce, reflections, crosstalk, and electromagnetic radiation. In an ideal world, one should limit the bandwidth so that the system performs to expectations, but at the same time, avoid high-frequency effects, which cause electromagnetic compatibility issues.

This is exactly what a series impedance termination does. The resistor, close to the source, combines with the in-put capacitance of the receiver IC(s) to create a low pass filter (Figure 2).

This filter rolls off the high-frequency components of the waveform, reducing reflections. Providing we choose the right value to match the impedance of the transmission line, the circuit functions perfectly, although the higher frequencies are dampened.

Depending on the logic family, the fall time is usually slightly shorter than the rise time. This is due to the design of typical CMOS out-put drivers. For the same feature size transistor, an N-type transistor can turn on faster than a P-type transistor. This means switching from high to low, the falling edge will be shorter than the rising edge. In general, signal integrity problems are more likely to occur when switching from a high-to-low transition than from a low-to-high transition. This is something to look out for when using double data rate (DDR) memory, where the device is clocked on both the rising and falling edges of the waveform.

To read this entire column, which appeared in the May 2020 issue of Design007 Magazine, click here.