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The Target Impedance Approach to PDN Design

Today’s high-performance processors employ low DC voltages with high transient currents and high clock frequencies to minimize the power consumption and hence the amount of heat dissipated. A typical high-speed design contains ten or more individual power supplies.

And unfortunately, the lower core voltages, higher currents and faster edge rates all impact on the power distribution network (PDN) design as well as signal integrity. The goal of robust PDN planning is to design a stable power source, taking the above into account, for all the required on-board power supplies. This month, I will look at the target impedance approach to PDN design.

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow. When I analyze a multilayer PCB, I immediately interpret the entire current loop including the return path by highlighting adjacent signal and associated plane layers. If you need to push a lot of current from one point to another, it is obvious where the hot spots will be. Increasing the plane copper thickness is a good solution, for DC and low frequency, but has little impact at high frequencies due to the skin effect. However, effective placement, the use of minimal antipads, and wide uninterrupted copper pours alleviates the issue before it arises.

The high clock frequencies and signal rates employed today push more of the physical board features into the red zone where their relative dimensions, with respect to the wavelength of the clock, approach or exceed the quarter-wave limit. Quarter-wavelength or longer structures may become effective electromagnetic radiators; therefore, the PDN has become one of the primary EMI risk factors for high-speed designers. It is generally accepted that the best way to avoid EMI radiation from PDNs is to ensure a resonance-free impedance profile. The resonance-free impedance profile also helps to minimize simultaneous switching noise (SSN) and jitter of high-speed signals, when the PDN serves as both a stable power source and signal reference.

In the early days of digital electronics, there was no such thing as PDN design. Instead, the focus was on the maximum number of 100nF (and the odd 47pF) capacitors that could be placed close to the ICs power pins. Connecting a capacitor by a thick trace to a 60 mil DIP power pad was easy—but try doing that with a dense BGA package. This approach was sufficient as long as the active devices did not generate significant transient noise spectrum above the series resonance frequency (SRF) of the decoupling capacitors. However, higher system speeds later created the need to design the PDN systematically, to meet tighter impedance requirements.  

To read this entire column, which appeared in the February 2018 issue of the Design007 Magazine, click here.