-
-
News
News Highlights
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLearning to Speak ‘Fab’
Our expert contributors clear up many of the miscommunication problems between PCB designers and their fab and assembly stakeholders. As you will see, a little extra planning early in the design cycle can go a long way toward maintaining open lines of communication with the fab and assembly folks.
Training New Designers
Where will we find the next generation of PCB designers and design engineers? Once we locate them, how will we train and educate them? What will PCB designers of the future need to master to deal with tomorrow’s technology?
The Designer of the Future
Our expert contributors peer into their crystal balls and offer their thoughts on the designers and design engineers of tomorrow, and what their jobs will look like.
- Articles
- Columns
Search Console
- Links
- Media kit
||| MENU - design007 Magazine
Estimated reading time: 1 minute

Beyond Design: PDN Planning and Capacitor Selection, Part 2
In last month’s column, PDN Planning and Capacitor Selection Part 1, we looked closely at how to choose the right capacitor to lower the AC impedance of the power distribution network (PDN) at a particular frequency. We also examined capacitor properties and types of capacitors that are readily available and touched on the target frequency approach for analyzing a PDN. This month we will continue on from there looking at the one-capacitor-value-per-decade and optimized value approaches.
Figure 4 shows the effect of using the one-value-per-decade approach where capacitors from each decade are added in parallel. Now to be fair, I have added three of each value from 100uF to 1pF to total 27 capacitors as the target frequency approach, in Figure 2, had a total of 29 capacitors. In this case, the impedance is below the target impedance from 10KHz to 110MHz.
Figure 4: One value capacitor per decade approach.
Notice how the combination of capacitors causes anti-resonant (parallel resonant) peaks where the higher frequency capacitor goes capacitive while the lower frequency capacitor is inductive. This occurs as the LC network produced by the combination is effectively a tank circuit that has parallel resonance at the crossing frequency. This happens each time a different value of capacitor is added. These peaks exceed the 60mΩ impedance of the V shape of the target frequency approach--some as high as 800mΩ below 1GHz which is 13 times higher than the target impedance. If an odd harmonic was to fall on that particular frequency, then emissions would also be very high at that frequency. From extensive simulations, I have noticed that there is a direct correlation between AC impedance peaks and electromagnetic radiation. In fact, if a board fails electromagnetic compliancy, emissions can be dampened by changing the capacitors to ones that have a self-resonant frequency (SRF) close to the radiating frequency.Read the full column here.Editor's Note: This column originally appeared in the January 2014 issue of The PCB Design Magazine.
More Columns from Beyond Design
Beyond Design: Key SI Considerations for High-speed PCB DesignBeyond Design: Electro-optical Circuit Boards
Beyond Design: AI-driven Inverse Stackup Optimization
Beyond Design: High-speed Rules of Thumb
Beyond Design: Integrated Circuit to PCB Integration
Beyond Design: Does Current Deliver the Energy in a Circuit?
Beyond Design: Termination Planning
Beyond Design: Dielectric Material Selection Guide