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Cadence and Samsung Foundry announced development of a full portfolio of Memory and Interface IP, and expanded certification of Cadence’s agentic AI digital, custom, 3D‑IC and system design and analysis (SDA) flows for Samsung Foundry’s second-generation 2nm process technology. This collaboration delivers a signoff‑ready platform for next‑generation AI infrastructure and physical AI designs across data center, edge and intelligent devices.
Building on the companies’ 2025 announcement of certified Cadence tools and IP on multiple Samsung Foundry nodes, including second-generation 2nm, this new multi-year agreement further broadens the Cadence® portfolio of Memory and Interface IP, including NVIDIA NVLink-C2C-enabled interconnect and CUDA-X GPU-accelerated libraries spanning high-speed SerDes, PCIe®, UCIe® and all leading memory interfaces on second-generation 2nm. It also deepens enablement of certified Cadence flows so ecosystem partners can implement large AI, HPC and advanced system designs with higher performance, lower power and faster time to tapeout.
“AI infrastructure and physical AI are pushing the industry into advanced node and 3D‑IC designs that demand far more capacity, integration and signoff confidence than ever before,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “With this next phase of our Samsung Foundry collaboration, we’re giving joint customers a production‑proven platform to deliver the next-generation of AI and HPC systems to market faster.”
“Customers are increasingly drawn to Samsung Foundry’s second-generation 2nm for leading‑edge AI designs that must keep pace with the exploding demand across AI infrastructure and emerging physical AI applications,” said Jongshin Shin, executive vice president and head of Foundry Design Platform Development at Samsung Electronics. “Our expanded Cadence partnership delivers a robust semiconductor and 3D-IC platform with advanced Memory, Interface IP and AI-optimized flows for superior performance, efficiency and innovation.”
Agentic AI EDA/SDA Platform and 3D-IC Design on Samsung Foundry’s Second-Generation 2nm
Cadence and Samsung Foundry deliver a comprehensive certified flow on second-generation 2nm, including Cadence’s Innovus™ Implementation System for digital implementation, Virtuoso® Studio for analog and custom design, Integrity™ 3D‑IC Platform for full 3D‑IC system planning and implementation, Voltus™ IC Power Integrity Solution for power integrity and system‑level power analysis, and Quantus™ Extraction Solution and Tempus™ Timing Solution for signoff.
Cadence enables key second-generation 2nm design features, including the Innovus system and Genus™ Synthesis Solution’s glitch power optimization in the place and route flow, and a smart hierarchical flow to achieve optimal performance, power, and area (PPA) and turnaround time (TAT).
Samsung 3D Cube-H design is enabled with a full system planning, implementation and signoff flow for hybrid copper bonding (HCB) technology, including Cadence Cerebrus® Intelligent Chip Explorer, Integrity 3D‑IC, Innovus Implementation, Voltus IC Power Integrity (ERA) and Pegasus™ Verification System. It includes silicon interposer auto-routing and optimization, and ensures tighter connectivity between analysis, signoff, and verification, with the Tempus and Pegasus solutions providing trusted, confident signoff.
Advancing NVLink-C2C Interconnect for Next-Generation AI Infrastructure
NVIDIA is leveraging Cadence and Samsung Foundry’s expanded advanced-node and 3D-IC platform to deliver high-bandwidth interconnect through NVIDIA NVLink-C2C and CUDA-X GPU accelerated capabilities—foundational technologies that power next-generation accelerated computing systems and strengthen the broader ecosystem’s ability to produce high-performance AI semiconductors.
“As AI workloads scale and system architectures grow more demanding, the semiconductor ecosystem depends on tools and platforms that can keep pace with simulation and design complexity at advanced nodes,” said Timothy Costa, vice president and general manager of computational engineering, NVIDIA. "By leveraging Cadence’s GPU-accelerated design flows on Samsung Foundry’s second-generation 2nm platform, we’re optimizing the performance and delivery of next-generation AI architectures and high-bandwidth interconnects.”
Enabling Ambarella’s Next-Generation Edge AI Platform
Ambarella is developing its next-generation 2nm edge AI platform to extend its leadership in high-performance, ultra-low-power AI perception and physical AI SoCs for intelligent edge systems spanning robotics, drones, autonomous machines, and advanced sensing applications.
“Ambarella’s edge AI strategy is focused on delivering industry‑leading performance per watt, scalable AI acceleration, and robust multi‑sensor processing at the most advanced process nodes,” said Chan Lee, chief operating officer at Ambarella. “Our collaboration with Cadence and Samsung Foundry to deliver IP for PCIe 5.0 for our next‑generation 2nm edge AI platform has been critical as we address the design, verification and manufacturing complexity of this node. Having a signoff‑ready, co‑optimized IP and tools solution, together with a robust, production‑proven design kit and PDK, enables our teams to move forward with confidence, reduce risk and stay focused on accelerating innovation in low‑power AI perception, physical AI and intelligent edge computing.”
Cadence and Samsung Foundry will highlight their enhanced partnership and design enablement during the Samsung Advanced Foundry Ecosystem (SAFE) 2026 event, featuring technical sessions and demonstrations showcasing second-generation 2nm and 3D-IC design flows for GPU-accelerated AI workloads.
