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Beyond the Rulebook
What happens when the rule book is no longer useful, or worse, was never written in the first place? In today’s fast-moving electronics landscape, we’re increasingly asked to design and build what has no precedent, no proven path, and no tidy checklist to follow. This is where “Design for Invention” begins.
March Madness
From the growing role of AI in design tools to the challenge of managing cumulative tolerances, these articles in this issue examine the technical details, design choices, and manufacturing considerations that determine whether a board works as intended.
Looking Forward to APEX EXPO 2026
I-Connect007 Magazine previews APEX EXPO 2026, covering everything from the show floor to the technical conference. For PCB designers, we move past the dreaded auto-router and spotlight AI design tools that actually matter.
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Tomachie Launches AI-Powered PCB Analysis with Smart Test Point Insertion
April 28, 2026 | TomachieEstimated reading time: 2 minutes
Tomachie announced its AI-Assisted PCB schematic design analysis platform, enabling engineering teams to evaluate and improve schematic quality before layout begins. Schematic errors caught after layout — or in production — cost 10 to 100 times more to fix than those caught during schematic capture. Supporting Altium, KiCad, and other schematic tools, Tomachie accepts privately encrypted design uploads for automated assessment of electrical intent and downstream readiness.
Schematic Design Quality
"Tomachie catches schematic errors, missing test points, during schematic capture, at the lowest cost to fix — before layout locks in decisions that cost 10 to 100 times more to correct later."
Tomachie handles any design complexity — flat, hierarchical, multi-sheet, harness-based, and bussed architectures — establishing a measurable quality baseline that reduces downstream friction across the product lifecycle. Library quality checks grade model correctness and verify IPC land pattern compliance. By enforcing schematic correctness without restricting architectural choices, Tomachie reduces repeat review cycles and minimizes interpretation errors during alternate part swaps, test generation, and production handoffs.
Electrical and Interface Verification
The platform performs over 400 automated design checks spanning low-speed serial interface (LSSI) verification — I²C pull-up validation, JTAG TAP selection, EMC shield-to-logic GND handling, SPI controller/target configuration, termination errors on clock lines, and output-enables tied directly to power/GND planes. High-speed serial interface (HSSI) nets are identified, avoided during intelligent test point insertion, and collated for engineering team documentation.
Automated Documentation Generation
Tomachie auto-generates document editor-ready tables of connector pinouts, power distribution summaries, I²C address maps, JTAG chain documentation, SPI controller/target tables, HSSI interface tables, and designer-annotated net documentation — reducing manual effort and improving communication with production, test, and non-technical stakeholders.
Structural Fault Coverage Analysis
Tomachie provides deterministic visibility into structural fault coverage across all major test methods — predicting solder fault coverage for manual inspection, AOI, and AXI; generating shorts and opens analysis using boundary scan (IEEE 1149.1, 1149.6, 1149.10) with and without loopback; and determining electrical fault coverage for flying probe, in-circuit, and Intellitech JAF® ATE using bed-of-nails or connector access.
Intelligent Test Point Insertion
A key differentiator is Tomachie's intelligent test point insertion engine. Based on user-defined policies and existing boundary scan access, it automatically identifies fault coverage gaps and inserts the required test points — giving layout teams precise guidance for area planning before the first component is placed. Policies support all-nets coverage, power rails only, and exclusions for HSSI and DDR memory. When not using a test-point-per-net strategy, the platform inserts test points where they deliver the most value.
Who Benefits
Design engineers catch substantive errors before they propagate. Engineering managers achieve consistent quality across in-house and contract designers. Production and test teams benefit from designs optimized for consistency, with functional testing focused on defects structural test cannot cover — all without anyone appearing pedantic about schematic correctness.
"Some may say 'experienced engineers don't make these mistakes.' In every design we've analyzed, we've found substantive issues — shell grounding errors, JTAG select problems, missing I²C pull-ups, passive values in comments, hidden NC pins, missing GND pins, non-compliant footprints – using imperial notation but metric dimensions. The tool doesn't replace experience; it catches what experience alone misses under schedule pressure and other factors," said CJ Clark, Co-Founder, Tomachie LLC.
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Sweeney Ng - CEE PCBSuggested Items
TRI Launches New Wafer Inspection and Metrology Platform
04/28/2026 | TRITest Research, Inc. (TRI), the leading provider of Test and Inspection solutions for the electronics manufacturing industry, is proud to announce the launch of the TR7950Q SII Series.
TTC-LLC and TTCI: Smarter Training, Stronger Test at PCB East 2026
04/27/2026 | The Test Connection Inc.The Training Connection LLC (TTC-LLC) and The Test Connection, Inc. (TTCI) will be exhibiting together at PCB East 2026, taking place April 28–May 1 at the DCU Convention Center in Worcester, Massachusetts. Attendees can find both teams at Booth #103 during the main exhibition day on Wednesday, April 29.
Design for Test: A New Book from The Test Connection, Inc.
04/23/2026 | Real Time with... APEX EXPOBert Horner, president of The Test Connection Inc., shares insights on designing for testability (DFT) challenges with Kelly Dack. Horner discusses the critical need for incorporating testability early in the design process and the importance of quantifiable metrics for measuring test coverage. He highlights The Test Connection's role in transferring decades of 'tribal knowledge' to emerging engineers through training and education. Look for "The Printed Circuit Assembler's Guide to... Design for Test, A Practical Guide to Test and Inspection" in the I-007eBooks library.
Würth Elektronik Expands Laboratory in Shenzhen, China
04/17/2026 | Wurth ElektronikWürth Elektronik eiSos Group celebrated the official opening of the Laboratory Phase II at its Asia Quality Design Center (QDC Asia) in Shenzhen on March 5, 2026.
Würth Elektronik Expands Laboratory in Shenzhen, China
04/16/2026 | Wurth ElektronikWürth Elektronik eiSos Group celebrated the official opening of the Laboratory Phase II at its Asia Quality Design Center (QDC Asia) in Shenzhen on March 5, 2026.