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Advancing Electrolytic Copper Plating for AI-driven Package Substrates
August 5, 2025 | Dirk Ruess and Mustafa Oezkoek, MKS’ AtotechEstimated reading time: 1 minute

Editor’s note: The following technical paper, originally titled “Cutting-Edge Pulse Plating Solutions for Uniform Deposition of Copper with Enhanced Reliability in State-of-the-Art Server Technology,” was first presented at IPC APEX EXPO 2025’s Technical Conference, with original work published within the conference proceedings.
The rise of artificial intelligence (AI) applications has become a pivotal force driving growth in the server industry. Its challenging requirements for high-frequency and high-density computing are leading to an increasing demand for development of advanced manufacturing methods of package substrates with finer features, higher hole densities, and denser interconnects. These requirements are essential for modern multilayer board (MLB) designs, which play a critical role in AI hardware. However, these intricate designs introduce considerable manufacturing complexities.
The Critical Role of Electrolytic Copper Plating
Electrolytic copper plating is a key process in package substrate manufacturing, significantly impacting subsequent stages such as etching. A major challenge in electrolytic plating is ensuring uniform copper distribution across the entire panel, whether in areas with a high density of holes or more isolated sections. Such high hole-density regions are integral to modern multilayer board (MLB) designs, despite introducing several manufacturing complexities. Traditional plating methods often result in inconsistent copper thickness across regions with varying hole densities, leading to discrepancies known as the “surface thickness gap.” This can lead to inconsistencies in etching and overall circuit performance. Moreover, achieving high throwing power is crucial to ensure sufficient copper is deposited within through-holes without excessive surface copper.
To continue reading this article, which originally appeared in the July 2025 issue of PCB007 Magazine, click here.
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Point2 Technology, Foxconn Interconnect Technology Partner to Revolutionize AI Cluster Scalability with Terabit-Speed Interconnect
08/06/2025 | BUSINESS WIREPoint2 Technology, a leading provider of ultra-low-power, low-latency mixed-signal SoC solutions for multi-terabit interconnect, and Foxconn Interconnect Technology (FIT), a global leader in precision interconnect solutions, have signed a Memorandum of Understanding (MOU) to accelerate the commercialization of next-generation Active RF Cable (ARC) and Near Pluggable e-Tube (NPE) solutions.
Statement from the Global Electronics Association on the July 2025 Tariff on Copper Foil and Electronics-Grade Copper Inputs
07/31/2025 | Global Electronics AssociationWe are disappointed by today’s decision to impose a 50% tariff on imported copper foil and other essential materials critical to electronics manufacturing in the United States.
Trouble in Your Tank: Metallizing Flexible Circuit Materials—Mitigating Deposit Stress
08/04/2025 | Michael Carano -- Column: Trouble in Your TankMetallizing materials, such as polyimide used for flexible circuitry and high-reliability multilayer printed wiring boards, provide a significant challenge for process engineers. Conventional electroless copper systems often require pre-treatments with hazardous chemicals or have a small process window to achieve uniform coverage without blistering. It all boils down to enhancing the adhesion of the thin film of electroless copper to these smooth surfaces.
Considering the Future of Impending Copper Tariffs
07/30/2025 | I-Connect007 Editorial TeamThe Global Electronics Association is alerting industry members that a potential 50% tariff on copper could hit U.S. electronics manufacturers where it hurts.
Connect the Dots: Sequential Lamination in HDI PCB Manufacturing
07/31/2025 | Matt Stevenson -- Column: Connect the DotsAs HDI technology becomes mainstream in high-speed and miniaturized electronics, understanding the PCB manufacturing process can help PCB design engineers create successful, cost-effective designs using advanced technologies. Designs that incorporate blind and buried vias, boards with space constraints, sensitive signal integrity requirements, or internal heat dissipation concerns are often candidates for HDI technology and usually require sequential lamination to satisfy the requirements.