Elementary, Mr. Watson: Rules of Thumb—Guidelines vs. Principles for PCB Design
Beyond Design: High-speed Rules of Thumb
Global PCB Connections: A Technical Overview of Long-flex Printed Circuit Boards
Cadence Wins Four 2023 TSMC OIP Partner of the Year Awards
October 20, 2023 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced that it has won four Open Innovation Platform® (OIP) Partner of the Year awards from TSMC for its EDA and IP design solutions. Cadence was presented with awards for the joint development of the N2 and N3P design infrastructure, 3Dbloxdesign prototyping solution, mmWave design solutions and DSP IP. The awards build upon the companies’ long-standing history of collaboration that has delivered many highly innovative SoC and advanced packaging design solutions to the global market.
The awards are based on the following TSMC collaborations:
- N2 and N3P Design Infrastructure: Cadence optimized its complete digital and custom/analog flows for the TSMC N2 and N3E process technologies to help customers achieve power, performance and area (PPA) goals and accelerate innovation. Additionally, Cadence’s AI-powered solutions, Cadence® Cerebrus™ Intelligent Chip Explorer and Virtuoso® Studio, support these nodes, offering customers innovative automation capabilities to make them more efficient.
- Joint Development of 3Dblox Design Prototyping Solution: Design flows based on the Cadence Integrity™ 3D-IC Platform support the TSMC 3Dblox standard for 3D front-end design partitioning in complex systems. The flows include system prototyping flows, which are optimized for all of TSMC’s latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC® ) technologies.
- Joint Development of mmWave Design Solutions: The new Cadence Virtuoso Studio was integrated into the TSMC N16 mmWave RF design reference flow and N6RF design reference flow, and support has been added for the N4P RF design reference flow. In addition, Cadence collaborated with TSMC to optimize the Virtuoso platform for the 79GHz mmWave design reference flow on TSMC’s N16 process.
- DSP IP: Cadence expanded its collaboration with TSMC’s Soft IP9000 team to certify Cadence Tensilica® DSP IP in the TSMC integration flow.
“TSMC works continuously with our OIP design partners to enable technology advancements that make it faster and easier for customers to deliver competitive designs to market, simpler for customers to adopt our solutions,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Cadence’s commitment to design excellence is exemplary, and the TSMC OIP Partner of the Year awards are a testament to their dedication to ongoing innovation.”
“By continuing to collaborate closely with TSMC, we’re constantly energized by the innovations our customers bring to life using our technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “It’s an honor to be recognized with these prestigious TSMC awards, and they are a testament to the work we’ve done to enable our customers to achieve their design and time-to-market goals.”
Share on:
Suggested Items
PCB Layout Rules of Thumb for Consideration
11/25/2024 | Patrick Davis, Cadence Design SystemsJust because a “rule of thumb” is usually based on experience instead of precise facts doesn’t negate its value. For instance, when I told my kids that a good rule of thumb was not to back-talk to their mother, they discovered very quickly how accurate my advice was once they crossed that line. There are a lot of rules of thumb that we rely on daily, including those that apply to PCB design.
HPC Customer Engages Sondrel for High End Chip Design
11/25/2024 | SondrelSondrel, a leading provider of ultra-complex custom chips, has announced that it has started front end, RTL design and verification work on a high-performance computing (HPC) chip project for a major new customer.
Rules of Thumb for PCB Layout
11/21/2024 | Andy Shaughnessy, I-Connect007The dictionary defines a “rule of thumb” as “a broadly accurate guide or principle, based on experience or practice rather than theory.” Rules of thumb are often the foundation of a PCB designer’s thought process when tackling a layout. Ultimately, a product spec or design guideline will provide the detailed design guidance, but rules of thumb can help to provide the general guidance that will help to streamline the layout process and avoid design or manufacturing issues.
PCB Design Software Market Expected to Hit $9.2B by 2031
11/21/2024 | openPRThis report provides an overview of the PCB design software market, detailing key market drivers, challenges, technological advancements, regional dynamics, and future trends. With a projected compound annual growth rate (CAGR) of 13.4% from 2024 to 2031, the market is expected to grow from $3.9 billion in 2024 to $9.2 billion by 2031.
KYZEN to Spotlight KYZEN E5631, AQUANOX A4618 and Process Control at SMTA Silicon Valley Expo and Tech Forum
11/21/2024 | KYZEN'KYZEN, the global leader in innovative environmentally friendly cleaning chemistries, will exhibit at the SMTA Silicon Valley Expo & Tech Forum on Thursday, December 5, 2024 at the Fremont Marriott Silicon Valley in Fremont, CA.