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Beyond Design: Ground Bounce

Ground bounce, or more precisely, supply bounce, is the voltage produced between two points in the power delivery path. It is fundamentally related to the total inductance of the current path and shared return paths and the instantaneous surge current delivered by the power supply. Once again, we find that inductance is the covert enemy of the high-speed PCB designer. It is the primary cause of simultaneous switching noise and electromagnetic radiation. As edge rates continue to increase, the impact of intrinsic electrical characteristics become more pronounced. One of these inherent characteristics is the inductance found in the supply leads of all ICs. In this month’s column, I will look at supply bounce and how to minimise the impact on high-speed digital circuits.

Ground bounce arises from a common-mode potential developed between an IC die substrate and the PCB ground return plane and is totally independent of the transmission line characteristics. The physical location of the device driver within the IC as well as the number of outputs that are simultaneously switched, with respect to the common power and ground connections to the die, also has an impact. In addition, ground bounce is associated with the dI/dt (change in current over time) of the output which depends on the switching speed of the driver gate.

Ground (GND) bounce is generated by high-to-low transitions of the signal, whilst power (VDD) bounce to generated by low-to-high transitions as in Figure 2. The output buffer stage of a CMOS device is an inverter; thus, the outputs are switching low-to-high when their inputs are switching high-to-low and vice versa. It is the current associated with switching the output transistors that generates ground bounce. Note that everything discussed here concerning ground bounce can equally be applied to the opposite effect: VDD bounce.

When supply bounce occurs, the charge that is impressed across the power delivery path results in common-mode voltage. Unfortunately, it is not possible to eliminate the transfer of charge between logic transitions but the magnitude of the radiated peaks can be limited by providing a very low AC impedance path between power and ground. This is why power distribution network (PDN) planning is so important. The AC impedance of the power planes must be maintained below the target impedance up to the maximum bandwidth.

The measured supply bounce is generally very small (typically 150mV) compared to the full rail voltage swing of the output signal. So, its presence does not impact on the transmitted signal. However, it does interfere with the reception of the signal at the load, depending on the noise margin, and can cause double clocking. This is because a TTL receiver compares the input voltage against the local 0V ground reference plane. CMOS devices compare the input voltage to the weighted average of the VDD and GND while ECL compares it to VDD. Although the topology is different between logic families, the concept of supply bounce is the same. If N outputs are simultaneously switched, then there is N times as much current and therefore the supply bounce pulse is N times larger.

To read this entire column, which appeared in the January 2018 issue of Design007 Magazine, click here.