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Beyond Design: PDN–Decoupling Capacitor Placement

The impact of lower core voltages and faster edge rates has pushed the frequency content of typical digital signals into the gigahertz range. Consequently, the performance of decoupling capacitors, that are required to complement the power distribution network (PDN) and curb signal induced fluctuations, must also be extended up into this range. However, rudimentary design rules, adequate for frequencies below 100MHz, may not be suitable for today's high-speed digital circuits. The symptoms of an inadequate PDN design are increased power supply noise, crosstalk and electromagnetic radiation leading to poor performance and possibly intermittent operation.

In most cases, conventional design guidelines recommend that the decoupling (or bypass) capacitors be placed on the bottom side of the PCB, under the BGA, for closest proximity to the IC. However, decoupling is not the process of placing a few random capacitors adjacent to each IC power pin. But rather, it is the process of placing an RLC network to supply the transient switching current and to provide a return current signal path back to the source. A capacitor’s equivalent circuit is basically a series capacitor, resistor and inductor as illustrated in Figure 1. These are referred to as the capacitance value, ESR and ESL respectively.

The primary design consideration is the parasitic series inductance of the capacitor itself and its associated mounting and via inductance. The parasitic series inductance of a decoupling capacitor acts like a small inductor in series with the capacitor. At higher and higher frequencies, the impedance of this parasitic inductance becomes larger and larger (Figure 1), until it finally dominates the performance of the component.

In the critical 100MHz–1GHz band, the effectiveness of a typical decoupling capacitor is determined almost entirely by its series inductance. This is the frequency band now being used increasingly by digital logic. For ideal performance, low series inductance is required. However, the series inductance of a capacitor is not only determined by its ESL, but rather almost entirely by the layout of the capacitor's mounting lands and its associated fanout vias. The exact location of the capacitor is unimportant (providing it is within a 2” radius of the IC) as the plane inductance is negligible. Every time the signal edge rates double, we become twice as dependent on these layout details. If a product radiates too much in this region, the most effective way to reduce noise is to improve the layout of the decoupling capacitor lands and to reduce the via loop area. Improving the layout reduces the effective inductance of the components, leading to a direct reduction in power and ground noise. It is the inductance of this current path that creates ground (supply) bounce. 

To read this entire column, which appeared in the January 2016 issue of The PCB Design Magazine, click here.