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For bare PCB board fabrication, defect reduction is a critical aspect of a company's bottom line profitability. In this issue, we examine how imaging, etching, and plating processes can provide information and insight into reducing defects and increasing yields.
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The Essential Guide to Surface Finishes
We go back to basics this month with a recount of a little history, and look forward to addressing the many challenges that high density, high frequency, adhesion, SI, and corrosion concerns for harsh environments bring to the fore. We compare and contrast surface finishes by type and application, take a hard look at the many iterations of gold plating, and address palladium as a surface finish.
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Design of Experiments
Figure 2: An example of factorial design of experiments (DOE) in printed circuit manufacturing to minimize innerlayer shifting during lamination.
The second experiment, in Figure 3, uses optimizing photoresist exposure, developing and etching to provide the highest production yield. The variable and levels were a full factorial design of three variables at three levels (center point):
1. Exposure energy in mjoules: 70, 50 & 30
2. Developer speed in inches per minute: 45, 40 & 35
3. Etcher speed in inches per minute: 45, 40 & 35.
The variables were chosen with the center point being the current production process: 50 mjoules, 40 in/min developer and 40 in/min etcher. The highest yield was 95% using slower developer speed, lower exposure intensity, and the slower etcher. Analysis shows that the developer speed has the greatest effect on yield and interacts with etcher speed.
Figure 3: An example of factorial design of experiments (DOE) in printed circuit manufacturing to optimize yield in exposure, developing and etch.
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