Advanced Packaging: A Central Axis of Innovation in Aerospace, Defense and Automotive

Estimated reading time: 5 minutes

Presenters in the Aerospace & Defense Special Session at APEX EXPO 2026 made one message abundantly clear: Advanced packaging has moved from a supporting role to a primary system enabler, particularly in high-reliability markets where performance, longevity, and environmental resilience are non-negotiable. 

The March Technical Conference at APEX EXPO focused on advanced electronics for the first time this year, with two Special Sessions featuring a carefully curated selection of presentations examining how design priorities, material choices, and manufacturing strategies are evolving in response to these demands.

Presenters for the aerospace and defense (A&D) session included Jason Milne of Raytheon Tehnologies; Mark Litecky of SkyWater Technology; Vijay Rentala, Analog Mixed-Signal Group, onsemi; Luc Ouellet of IBM; and Jan Vardamen of TechSearch Inc.

APEX EXPO is hosted by the Global Electronics Association and Special Sessions proceedings are available exclusively to attendees.

Below is a brief overview of some of the presentations from the exclusive event.

“Microelectronics Packaging for Aerospace, Defense, and Automotive” was led by Jason Milne of Raytheon, Mark Litecky of SkyWater Technology, and Vijay Rentala of onsemi. A central theme of their discussion was the stark divergence between consumer electronics, A&D, and automotive systems. While commercial devices are optimized for cost and scale, A&D and automotive platforms must meet stringent reliability requirements under extreme operating conditions.

These systems are expected to function across wide temperature ranges (−20°C to 150°C), withstand mechanical shock and vibration, and maintain performance over lifecycles extending 10–15 years or longer.

Under these conditions, failure is not an acceptable outcome; it is a design flaw to be engineered out at every level. The optimization framework—often summarized as SWaP-C for size, weight, power, and cost—takes on added complexity in these environments. Being able to reduce the system footprint while increasing functionality requires a system-level approach that tightly integrates packaging, interconnects, and materials with device architecture.

Application Drivers and Technology Limits

Some of the key applications discussed during this session on microelectronics packaging included wideband RF systems, phased arrays, focal plane arrays, and compact power converters. In each case, performance requirements are driving packaging innovation.

For phased arrays, the physical spacing of elements is constrained by wavelength, leaving little flexibility for component placement. This drives the need for highly integrated front-end modules. Similarly, automotive ADAS systems demand compact, high-reliability packaging capable of operating across wide environmental ranges while supporting increasing computational loads.

The accelerating shift toward heterogeneous integration (HI) as the dominant architectural paradigm for many advanced electronic systems is being driven by applications such as phased-array radar, SATCOM, and ADAS that demand higher functional density within constrained form factors.

For example, in wideband digital phased arrays, the move from analog to digital architectures is pushing analog-to-digital (A/D) signal processing closer to the antenna, creating significant spatial and thermal challenges that traditional board-level approaches struggle to meet. In answer to this, 2.5D and 3D packaging technologies enable vertical and lateral integration of diverse die types using silicon interposers, micro-bumps, and chiplet architectures, preserving signal integrity while minimizing parasitics.

This evolution is driving a convergence between semiconductor and package design (advanced electronic packaging), blurring traditional boundaries, and necessitating full-stack co-design methodologies.

Not all emerging technologies, however, are universally applicable. Panel-level packaging (PLP), while attractive for high-volume commercial applications, does not align well with the low-volume economics of A&D. This highlights the need for technology selection that closely matches production scale and application requirements.

Materials and Interconnect Transitions

In semiconductors, the transition from ceramic to organic substrates represents a significant shift in packaging materials. While ceramics have historically provided superior thermal and mechanical stability, organic substrates offer advantages in scalability, cost, and electrical performance when paired with advanced interconnect schemes.

Similarly, the migration from wire bonding to flip-chip , Cu Pillar and micro bump based  assemblies is enabling higher I/O density and improved electrical characteristics. Reduced interconnect lengths result in lower inductance and resistance, which are critical for high-frequency and high-power applications.

System-in-package (SiP) architectures further extend these capabilities by integrating multiple functional elements—often on both sides of a substrate—into a single, compact module. For aerospace and defense applications, SiP offers a viable pathway to replace traditional multi-board assemblies, improving performance and reducing overall system footprint.

Supply Chain Constraints and Strategic Risk

Presenters highlighted the growing disconnect between global state-of-the-art packaging capabilities and what is available domestically in the United States. For applications subject to ITAR and other regulatory controls, this gap represents both a technical and strategic risk. Critical elements such as advanced laminate substrates, high-density interconnect PCBs, and non-lead-based bumping processes are often difficult to source domestically. The production profile typical of A&D—low volume, high mix—does not align with the high-throughput models that dominate commercial manufacturing, creating additional challenges around cost and scale.

Compounding these challenges is component obsolescence. Programs that span decades must contend with supply chains optimized for rapid product turnover. Mitigation strategies such as last-time buys and forward purchasing are increasingly necessary, but they introduce costs, storage, and forecasting complexities that must be managed early in the program lifecycle.

Rebuilding Domestic Capability

To address supply chain vulnerabilities, some presenters announced some initiatives underway to expand domestic advanced packaging capabilities:

• DARPA’s Microelectronics Manufacturing Development (MDM) program is establishing infrastructure at the Texas Institute of Electronics (TIE) to support low-volume, high-mix heterogeneous integration. The program aims to bridge the gap between research and production, with a timeline extending through 2029.
• Raytheon is developing a complementary approach through its wafer-based turnkey manufacturing service, designed for prototyping and specialized applications. Delivered via the MOSIS platform as “GW Run,” the service is expected to provide access to advanced packaging capabilities starting with pilot runs in 2026.
• IBM’s contribution centers on its ITAR-certified facility in Markham provide end-to-end support from early-stage R&D through high-volume manufacturing. The company is advancing interposer technology with a 10/10-micron process and exploring new architectures such as the Molded Interposer Package (MIP), which integrates bridge die and memory within a molded structure to achieve high-density interconnect.
• Domestic capabilities for A&D from onsemi and SkyWater.

Lifecycle Integration and Co-Design

A consistent message across this Session was the importance of integrating packaging considerations early in the design process. As system complexity increases, late-stage adjustments are both costly and ineffective. Co-design is becoming essential, including die and package co-design, thermal and electrical modeling, and integrated testing. This helps to provide comprehensive lifecycle support.

Equally important is the feedback loop from manufacturing and field performance back into design, enabling continuous refinement and improved reliability over time. Early collaboration between system designers, packaging engineers, and manufacturing partners is increasingly viewed as a prerequisite for success, particularly in programs with long lifecycles and stringent performance requirements.

Conclusion

The convergence of heterogeneous integration, material advancements, and system-level co-design is enabling new levels of performance, but also introducing new complexities in supply chain management, manufacturing, and lifecycle support. As the industry works to close domestic capability gaps and adapt to these evolving demands, the role of packaging will continue to expand. For engineers and program managers alike, packaging is no longer an afterthought; it is the system.

For more information on the individual APEX EXPO presentations and presenters, or to please contact Tracy Riggan or Devan Iyer. To purchase conference proceeds, click here.