Advanced Electronic Packaging: How the Global Electronics Association Is Addressing Challenges and Needs in Malaysia
January 19, 2026 | Devan Iyer and Matt Kelly, Global Electronics AssociationEstimated reading time: 3 minutes
Editor’s Note: The original version of this post can be viewed here.
By Matt Kelly, CTO and VP Standards & Technology, and Devan Iyer, Chief Strategist, Advanced Electronic Packaging, Global Electronics Association
In November, more than 200 industry leaders, including government officials, regional domestic companies, multinational companies, and academic experts, gathered at the Olive Tree Hotel in Penang for the Advanced Electronic Packaging (AEP) Workshop, organized by the Global Electronics Association. With 15 expert speakers, three technical tracks, three expert panel discussions, and strong ecosystem participation, the workshop highlighted why advanced electronic packaging is central to the future of Malaysia’s semiconductor industry. Noting this as a "critical moment for Malaysia's electronics ecosystem," the Association also highlighted the need for new guidelines and standards as well as greater collaboration within the ecosystem, among stakeholders.
Why Advanced Electronic Packaging Matters to Malaysia’s Semiconductor Growth
Advanced electronic packaging is now a foundational enabler for many of today’s most advanced technologies, including AI systems, 5G/6G infrastructure, electric and autonomous vehicles, IoT, and sensor fusion platforms. As performance demands increase, traditional packaging approaches are no longer sufficient for meeting power density, data transmission, thermal efficiency, miniaturization, and reliability requirements.
This shift has accelerated the adoption of chiplet architectures, heterogeneous integration, and 2.5D/3D packaging. For Malaysia, a global hub for assembly and test, these developments represent a major strategic opportunity. The nation has built many decades of semiconductor packaging manufacturing capabilities and capacities, especially in analog and mixed signal (AMS) and power packaging technologies. This foundation positions Malaysia to expand its footprint in next-generation AMS and power packaging, while also leveraging high-performance computing (HPC) opportunities driven by AI servers, accelerators, and advanced memory technologies.
A Crucial Moment for Malaysia’s Electronics Ecosystem
Malaysia’s semiconductor landscape is shifting toward deeper technology integration and system-level innovation. Applications like EV power modules, mmWave radar, LIDAR, and AI accelerators require coordinated advances in both component-level packaging (CLP) and system-level packaging (SLP).
As these developments accelerate, the need for new industry guidelines and globally aligned standards grows rapidly. Protecting intellectual property remains essential, but shared industry challenges require common frameworks.
New guidelines and standards are critical to:
- Strengthen supply-chain continuity and reduce disruptions
- Improve interoperability across suppliers and partners
- Ensure consistent, scalable, and reliable manufacturing
- Help maintain competitive cost structures
Malaysia’s expansion into both AMS, Power, and HPC packaging amplifies the importance of developing such standards locally and globally.
Why the AEP Workshop in Penang Was So Important
The workshop delivered deep technical insight across topics, including:
- Chip and interposer design for High Bandwidth Memory (HBM) packaging
- Chiplet and heterogeneous integration
- 2.5D/3D packaging for AI, HPC and HBM packaging
- AI-enabled assembly, inspection, and automation
Participants emphasized the value of the event’s “silicon-to-systems” approach, which mirrors the realities of today’s integrated electronics architectures, and reinforces the need for updated industry standards to support this evolution.
Strengthening Collaboration Through the MAPC Consortium
A major milestone of the event was the launch of the Malaysia Advanced Packaging Consortium (MAPC). This consortium unites government, regional domestic companies, MNCs, and R&D partners to:
- Accelerate advanced packaging capability in Malaysia
- Share R&D priorities, common challenges and best practices, and strengthen ecosystem alignment
- Shape the guidelines and standards the industry urgently needs
Looking Ahead
As global technology advances, advanced electronic packaging and strong industry standards will define the next era of electronics manufacturing. The Penang AEP Workshop showcased Malaysia’s willingness to lead, building on decades of packaging strength while expanding into AMS, Power, and HPC opportunities.
The Global Electronics Association remains committed to supporting this journey through knowledge sharing, the development of guidelines and standards, and community building.
Subscribe
Stay ahead of the technologies shaping the future of electronics with our latest newsletter, Advanced Electronics Packaging Digest. Get expert insights on advanced packaging, materials, and system-level innovation, delivered straight to your inbox.
Subscribe now to stay informed, competitive, and connected.
Suggested Items
MacDermid Alpha to Address Silver Price Volatility Solutions at ECTC 2026
05/15/2026 | MacDermid AlphaAs volatile silver prices continue to place pressure on semiconductor packaging costs and supply chain predictability, MacDermid Alpha Electronics Solutions will highlight material strategies that help manufacturers reduce dependence on silver without sacrificing reliability, thermal performance, or manufacturing efficiency.
What Heterogeneous Integration Means for EMS Providers
05/14/2026 | Nolan Johnson, I-Connect007Dr. Ravi Mahajan, an Intel Fellow and Director of Intel’s Technology and Pathfinding group, delivered a keynote at the APEX EXPO 2026 technical conference on using heterogeneous integration (HI) as a strategy and on how advanced packaging technology serves as the technical apex for implementing that strategy. Mahajan’s previous papers and industry presentations on such topics as interconnect density, signal integrity, power delivery, thermal path, and assembly yield as system-level constraints confirm him as an expert on package optimization.
System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor
05/14/2026 | Chetan Arvind Patil, Marvell TechnologyIn conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.
I-Connect007 Announces Upcoming Issue of Advanced Electronics Packaging Digest
05/13/2026 | I-Connect007The next issue of Advanced Electronics Packaging Digest examines the materials, architectures, and integration strategies shaping the next phase of electronics innovation, from reinforcement materials under thermal and frequency pressure to heterogeneous integration and advanced packaging as a system-level scaling factor.
ASE, WUS Announce Strategic Collaboration to Build Advanced AI Packaging Hub in Kaohsiung
05/08/2026 | ASE GroupAdvanced Semiconductor Engineering, Inc. (ASE) and WUS Printed Circuit Co., Ltd. (WUS) announced today a strategic collaboration for the construction of a state-of-the-art manufacturing facility in the Nanzih Technology Industrial Park, Kaohsiung.