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Trouble in Your Tank: Minimizing Small-via Defects for High-reliability PCBs
To quote the comedian Stephen Wright, “If at first you don’t succeed, then skydiving is not for you.” That can be the battle cry when you find that only small-diameter vias are exhibiting voids. Why are small holes more prone to voids than larger vias when processed through electroless copper? There are several reasons.
There are several reasons for small hole voiding when considering only the electroless copper process. Massive voiding is visible in Figure 1. The fabricator did not have voiding issues with holes greater than 13 mils in diameter. However, smaller-diameter vias, as seen in Figure 1, were prone to coverage issues. The panel in Figure 1 is 0.153" thick with a 0.010" diameter via. This is not particularly an issue with today’s advanced circuit board designs.
- Major causes of the defect include:
- Hydrogen gas bubbles lodging in vias
- Drill gouges in via
- Protruding glass fibers
- Excessive etchback
- Drilling burrs
- Drill debris
- Insufficient fluid flow through vias (either in catalyst or electroless copper solution)
- Poor rinsing after each chemical processing step
- Insufficient micro-roughening of the resin
- Poor catalyst adsorption
- Solution surface tension: need to improve wetting of the hole wall with plating solution
- Ineffective interaction between the catalyst and the electroless copper process—a process formulation issue
Addressing the bullet points in bold, the need to build high-density, high-reliability PWBs with small diameter vias is driven by the PC designer concerned with increased functionality and a smaller footprint. Since SMT is the key manufacturing method for component mounting, designers are no longer limited to the minimum via diameter for component insertion. Certainly, higher aspect ratio vias are more prone to voiding, as highlighted above.
Essentially, one can reasonably assume that small hole voiding is largely attributed to insufficient fluid flow through the via and gas bubble entrapment during the deposition process provided that all other processes have been optimized to maximize hole coverage. Solution flow through a hole is typically induced, creating a pressure differential across the through-hole. Solution flow is reduced as hole diameters decrease and board thicknesses increase. Solution flow can decrease sufficiently to cause voids. Another issue that leads to voids is hydrogen gas bubble entrapment. The gas bubbles from hydrogen gas generation are a by-product of the electroless copper deposition reaction. The air bubbles become entrapped when the solution movement is unable to displace the bubbles.
A companion cause of gas bubble entrapment is the surface energy of the electroless copper plating solution. Basically, the gas bubbles tend to localize in low-energy areas of the solution. This is referred to as high surface tension. By lowering the surface tension, you can reduce the size of the bubble, making it easier to dislodge the bubble from the hole.
A key aspect of minimizing defects due to gas bubbles is to create an environment whereby gas bubbles formed are much smaller and thus more easily dispersed. This includes engineering the electroless copper process to reduce bubble size and reduce surface tension (thereby increasing surface energy). In doing this, you can minimize the size of the bubbles before they coalesce into larger ones. Figure 2 shows a high aspect ratio hole processed through an optimized electroless copper process.
The printed wiring board industry has typically addressed small hole voiding in several ways, some of which can adversely affect reliability, including:
- Double passing through the electroless copper solution
- Increased work bar agitation
- Angling the panels in the plating rack to facilitate gas bubble removal
- Vibration agitation on the flight bar
- Bump agitation accomplished with the use of a lifter and cam assembly located beneath the flight bar. The lifter provides one bump per agitation stroke cycle.
- Increased panel spacing between the panels in the rack to facilitate solution flow
In most cases, these solutions solve small-hole voiding. However, beware of the detrimental effects when implementing these options.
Of grave concern is the option to “double-pass” PWBs with small-diameter vias through the electroless process. Fabricators claim that by doing so, they can eliminate the voids. It is important to understand that double-passing through the electroless copper increases the likelihood of cohesive failure of the copper deposit. Extreme care should be taken to ensure interconnect integrity is not compromised. Regardless, double-passing increases production time and cost.
The best defense against small hole voiding is optimizing processes that have a direct effect on the quality of plating in the via. These include drilling, desmear, catalyzation, and the electroless copper process itself.
This column originally appeared in the August 2025 issue of PCB007 Magazine.
More Columns from Trouble in Your Tank
Trouble in Your Tank: Metallizing Flexible Circuit Materials—Mitigating Deposit StressTrouble in Your Tank: Can You Drill the Perfect Hole?
Trouble in Your Tank: Yield Improvement and Reliability
Trouble in Your Tank: Causes of Plating Voids, Pre-electroless Copper
Trouble in Your Tank: Organic Addition Agents in Electrolytic Copper Plating
Trouble in Your Tank: Interconnect Defect—The Three Degrees of Separation
Trouble in Your Tank: Things You Can Do for Better Wet Process Control
Trouble in Your Tank: Processes to Support IC Substrates and Advanced Packaging, Part 5