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Beyond the Rulebook
What happens when the rule book is no longer useful, or worse, was never written in the first place? In today’s fast-moving electronics landscape, we’re increasingly asked to design and build what has no precedent, no proven path, and no tidy checklist to follow. This is where “Design for Invention” begins.
March Madness
From the growing role of AI in design tools to the challenge of managing cumulative tolerances, these articles in this issue examine the technical details, design choices, and manufacturing considerations that determine whether a board works as intended.
Looking Forward to APEX EXPO 2026
I-Connect007 Magazine previews APEX EXPO 2026, covering everything from the show floor to the technical conference. For PCB designers, we move past the dreaded auto-router and spotlight AI design tools that actually matter.
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Estimated reading time: 9 minutes
Conversations with...HSIO President Jim Rathburn
Rathburn: By using thin LCP dielectric layers in the 15 to 75 micron range, we can hit a sweet spot for single ended or differential impedance tuning with much tighter tolerance and truer match with lines and spaces in the same range and maintain an aspect ratio conducive to solid copper vias. With the fusion bonding process resulting in an essentially 3D matrix of high-speed circuits and vias completely surround by a common low-dielectric constant and eliminated lossy solder mask, we have seen significant signal integrity improvements over conventional construction beyond 40 GHZ. Another big advantage is the capacitive loading effects are much easier to manage which is important for many of the low-power architectures. The fusion process also allows for embedded passive function that can be a big benefit for signal conditioning and tuning with potential SMT component reduction near the high-density regions.The graphic below shows basic design rules for single-ended circuit construction tuned with the LCP design rules. These principles are an example, and apply to differential lines as well as microstrip designs as appropriate..jpg)
You can see there is opportunity to improve the performance of existing designs with larger line and space geometries with extension to line and space reduction to improve routing capability and layer count, providing several generations of line and space reduction as the customers adopt our design rules.
Beaulieu: Can you tell us how you developed this process?Page 2 of 4
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