Marcy’s Musings: Operating Without a Rulebook
It’s Only Common Sense: Hire for Hunger, Train for Skill
Dan’s Biz Bookshelf: ‘The 'NVIDIA Way: Jensen Huang and the Making of a Tech Giant’
Staying on Top of Signal Integrity Challenges
September 16, 2025 | Andy Shaughnessy, Design007 MagazineEstimated reading time: 1 minute
Over the years, Kris Moyer has taught a variety of advanced PCB design classes, both online IPC courses and in-person classes at California State University-Sacramento, where he earned his degrees in electrical engineering.
Much of his advanced curriculum focuses on signal integrity, so we asked Kris to discuss the trends he’s seeing in signal integrity today, the SI challenges facing PCB designers, and his go-to techniques for controlling or completely eliminating SI problems.
Andy Shaughnessy: Kris, your advanced design classes focus quite a bit on signal integrity. What SI issues are giving your students the most trouble today?
Kris Moyer: We actually cover signal integrity in all the IPC design courses except Introduction to PCB Design 1. Several SI issues come up in the classes fairly often. First is the problem of reflections and the associated overshoot and undershoot caused by impedance discontinuity in the transmission line design. The other issue that comes up quite frequently is how to design the power distribution system, including the selection of the decoupling capacitors to minimize the ground bounce/VCC bounce that happens during the switching events of modern digital systems.
Shaughnessy: Silicon geometries are likely to continue to keep shrinking. What effects do these shrinking features have on the PCB designer’s job?
Moyer: In my Professional Development course at APEX EXPO, I discuss that as silicon geometries of the devices continue to shrink, the rise/fall time of the digital signals will continue to get faster (decrease in time). This, in turn, will cause the frequency content in the square wave to increase. So, instead of the traditional 10–15 harmonics of the fundamental frequency we think of for traditional square waves, with these faster rise/fall times, we are now seeing harmonics of 50, 100, 200, or more of the fundamental frequency being necessary to create the sharp edge of the faster rise/fall times.
To continue reading this interview, which originally appeared in the September 2025 edition of Design007 Magazine, click here.
Share on:
Testimonial
"Advertising in PCB007 Magazine has been a great way to showcase our bare board testers to the right audience. The I-Connect007 team makes the process smooth and professional. We’re proud to be featured in such a trusted publication."
Klaus Koziol - atgSuggested Items
Spirit Electronics Named Authorized Distributor for Microchip Technology
04/17/2026 | Globe NewswireSpirit Electronics, a vertically integrated electronics design and manufacturing solutions provider serving the military and aerospace markets, announced that it has been designated as an authorized distributor for the Americas for Microchip Technology, a broadline supplier of semiconductors committed to making innovative design easier through total system solutions.
Cadence, NVIDIA Expand AI & Accelerated Computing Partnership
04/17/2026 | Cadence Design Systems, Inc.At CadenceLIVE Silicon Valley 2026, Cadence announced an expanded partnership with NVIDIA to deliver accelerated solutions across agentic AI, physics-based simulation and digital twins to unlock new levels of productivity and accelerate next‑generation engineering design flows across semiconductor design, physical AI systems and hyperscale AI factories.
Teradyne Acquires TestInsight, Accelerating Time to Market for AI and Data Center Devices
04/16/2026 | BUSINESS WIRETeradyne, Inc., a leading provider of automated test equipment (ATE) and advanced robotics, announced it has acquired TestInsight, a leading provider of semiconductor test development, validation, and conversion software widely used across the industry.
Cadence, Google Scale AI Chip Design with ChipStack on Google Cloud
04/16/2026 | Cadence Design SystemsCadence, an industry leader in AI-driven computational software for semiconductor and system design, announced a strategic collaboration with Google to optimize the Cadence® ChipStack™ AI Super Agent with Gemini on Google Cloud.
ESD Alliance Reports Electronic System Design Industry Posts $5.5 Billion in Revenue in Q4 2025
04/15/2026 | SEMIElectronic System Design (ESD) industry revenue increased 10.3% to $5,466.3 million in the fourth quarter of 2025 from the $4,955.2 million registered in the fourth quarter of 2024, the ESD Alliance, a SEMI Technology Community, announced today in its latest Electronic Design Market Data (EDMD) report.