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Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design
December 1, 2023 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution. This accomplishment marks a turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology. The team also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.
One of the most notable aspects of Samsung Foundry’s achievement was the team’s use of the Tempus ECO Option within the Cadence Innovus™ Implementation System, which facilitated faster design convergence and closure, leading to an unprecedented reduction in project timeline. Further contributing to the productivity improvement, Samsung Foundry deployed the Tempus hierarchical static timing analysis feature, enabling hierarchical design closure while optimizing resource allocation and reducing machine and memory demands. Lastly, the Samsung team utilized Tempus and Quantus distributed technology to curtail the overall runtime for this complex design.
“The successful tapeout of our SF5A design for 5G networking was a significant milestone for our team, and the enhanced efficiency and reduced runtime afforded by the Cadence Quantus Extraction Solution and Tempus Timing Solution are a testament to the power of innovation and collaboration between the Cadence and Samsung teams,” said Sangyun Kim, Vice president and head of Foundry Design Technology Team at Samsung Electronics. “We’re committed to pushing the boundaries and leveraging the effectiveness of these signoff tools to deliver our designs to market faster, and we look forward to building upon our success for future projects and advancements.”
“The integrated Quantus Extraction Solution and Tempus Signoff Solution played a pivotal role in enabling Samsung Foundry to achieve enhanced productivity and PPA gains and time-to-market efficiencies,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “The most rewarding aspect of the collaboration with Samsung Foundry was seeing the team achieve their target design metrics while accelerating the time to market. We’re looking forward to continuing our work together to advance innovation.”
The Quantus Extraction Solution and Tempus Timing Solution are part of the broader Cadence digital full flow, offering a faster path to tapeout. The tools and flow support the company’s Intelligent System Design™ strategy, enabling customers to achieve SoC design excellence.
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The Global Electronics Association Launches Design Village at APEX EXPO 2026
09/02/2025 | Global Electronics AssociationAPEX EXPO, the hallmark electronics tradeshow hosted by the Global Electronics Association, announced the launch of the Design Village, a new feature in the exhibit hall that will unite the world’s leading innovators and showcase next-generation solutions for the electronics industry.
Mastering PCB Floor Planning
08/28/2025 | Stephen V. Chavez, Siemens EDAPlacement of PCB components is far more than just fitting components onto a board. It’s a strategic and critical foundational step, often called “floor planning,” that profoundly impacts the board’s performance, reliability, manufacturability, and cost. Floor planning ties into the solvability perspective, with performance and manufacturability being the other two competing perspectives for addressing and achieving success in PCB design.
Elementary Mr. Watson: Routing Hunger Games—May the Traces Be Ever in Your Favor
08/26/2025 | John Watson -- Column: Elementary, Mr. WatsonI’d like to share a harsh truth, and I say this as a friend: PCB designers are often their own worst enemy. It’s rarely the complexity of the circuit, the last-minute changes from mechanical, the limited enclosure space, or the ever-expanding list of design rules that send projects to the dust heap of failed boards. More often, it's our own decisions, made too quickly and narrowly, and with too little foresight, that sabotage an otherwise good design.
Target Condition: Floor Planning Without a Floor
08/27/2025 | Kelly Dack -- Column: Target ConditionBy a show of hands, how many PCB designers have been asked to start a layout without a board outline, keep-out zones, or even height constraints? How many have had to work within a specific enclosure before the schematic was finalized? If this sounds familiar, you're not alone. Starting a PCB layout without critical constraints is like hiring an interior designer to buy furniture and carpet for a house you haven’t even purchased yet, or, even worse, trying to fit four bedrooms' worth of furniture in a one-room cabin.
I-Connect007 Editor's Choice: Five Must-Reads for the Week
08/22/2025 | Andy Shaughnessy, I-Connect007In this week’s roundup, we have a variety of articles covering design, manufacturing, sustainability, and, of course, tariff negotiations. We have a milestone anniversary to celebrate as well, with Dan Beaulieu about to publish his 1,000th column. When does Dan even sleep? Here’s to hoping that we have 1,000 more weeks of "It’s Only Common Sense."