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Defense Speak Interpreted: PCB-related OTAs from NAVSEA Crane

In my previous column, I described how Other Transaction Authority (OTA) projects were speeding up the development of new technology for the Defense Department. Much of this improvement has to do with the speed of contracting and the less restrictive selection and payment process involved. Specifically, I would like to call out projects under the National Security Technology Accelerator (NSTXL).

From the NSTXL charter, “NSTXL offers a unique and simplified approach to rapidly identify, develop, and transition technologies that address a range of operational and installation challenges for the U.S. Department of Defense (DoD), from individual warfighter technology to large-scale defense systems.”

While this description seems to allow an almost limitless number of technology developments, NSTXL is based in Raleigh, North Carolina—not Washington, D.C. There are over 500 members of NSTXL, across three major focus areas: The Training and Readiness Accelerator (TreX, a training and readiness accelerator affiliated with the U.S. Army), the Defense Technical Information Center (DTIC) Energy, and Strategic and Spectrum Missions Advanced Resilient Trusted Systems (S 2 MARTS).

The most important focus area for printed circuits is S 2 MARTS. This effort is focused at Naval Surface Warfare Center in Crane, Indiana. The thrust of S 2 MARTS is to “enable broader DoD access to commercial state-of-the-art (SOTA) EMS technologies, advanced microelectronics, radiation-hardened (RAD-HARD), and strategic missions hardware.” The key here is the advanced microelectronics effort.

NSWC Crane’s quoted objectives in establishing this OTA are as follows:

• “To develop a relationship with industry and academia to establish streamlined processes for obtaining innovative, SOTA technologies”
• “To establish an agile and collaborative working relationship amongst the government and academia/industry”
• “To establish a consortium comprised of entities possessing significant technical capabilities to meet government needs associated with technology areas of need”
• “To provide services, such as attracting, vetting, selecting, and retaining members, relevant to technology areas of need”

The first OTA award related to printed circuits was in response to “S 2 MARTS Project 19-04: Very High-Density Interconnects.” In their own words:
“This project will seek proposals for the development of prototype processes and materials for the manufacturing of very high-density substrate, interposer, and redistribution layer electronic device packaging interconnect products using polymer-based substrate materials. The prototype processes and materials will promote the use of and be integrated into the existing printed circuit board manufacturing facility at NSWC Crane utilizing standard printed board manufacturing equipment to the greatest extent possible while facilitating the capability to manufacture very high-density interconnects (VHDI). Proposed processes and materials should produce next-generation technologies, resulting in the capability for manufacturing very high-density, high-complexity substrate, interposer, and redistribution layer interconnects for high-reliability printed board and integrated circuit packaging products, ultimately yielding circuit features sizes of 5 micrometers (μm) or smaller. Awarded to Averatek, 550 Nuttman St., Santa Clara, California, 95054.”

The proposal deadline was mid-June 2019, with an award date in mid-September, 2019. This three-month award process was remarkably short by traditional DoD contract award standards. The project effort was disclosed publicly at IPC APEX EXPO in February.

This is envisioned as a four-phase project with the following objectives, disclosed in the solicitation (Table 1).

Each phase will require a technical data package, as well as 35 prototype devices for DoD testing. The initial funding for the project is $250,000, but more funding is reportedly available. As outlined in my previous column on OTAs, this effort requires one of the following conditions:

• A non-traditional defense contractor
• All small businesses participating
• One-third non-DoD funding from the participants

Another key to developing this technology effort is that NSWC Crane has the support of the Office of Secretary of Defense (OSD) for “Microelectronics Innovation for National Security and Economic Competitiveness (MINSEC).”

A more advanced, electronic interconnection technology award is the “SOTA Heterogeneous Integrated Packaging (SHIP) Prototype Project.” From the proposal:
“The Navy desires to develop a SOTA heterogeneous integrated packaging (SHIP) prototype to demonstrate the enhanced fabrication and packaging access for DoD programs. The primary objective of the SHIP prototype project will be to demonstrate a novel approach to a secure, assessable, and cost-effective SOTA-integrated design, assembly, and test, leveraging the expertise of the commercial industry. In addition, a SHIP prototype will achieve less power consumption and latency, also reducing physical size and improving performance and reliability.

Achieving the objective will require novel and innovative methods, including unique and secure design tools and intellectual property for multi-die heterogeneous integration of SOTA microelectronics. Secure SOTA fabrication, assembly, and test resources will also be developed to support the successful demonstration of the SHIP prototype that is International Traffic in Arms Regulations (ITAR) compliant.”

SHIP proposals were submitted on August 6, and the contract has just been awarded to a team consisting of GE Research, Intel Federal LLC, Keysight Technologies, Northrop Grumman Aerospace Systems, Qorvo, and Xilinx. This two-month award period is even shorter than the very high-density interconnects project!

The SHIP project also has four phases, but they are different from high-density interconnects. Phase one is a planning report, due within six months of contract award. Phase two is the development of a prototype facility and planning for production. Phase three is the installation and qualification of the prototype facility, and phase four is the operation of the facility for advanced interconnection devices.

SHIP could develop into a huge effort, with $25 million allocated just for phase one. Further funding is indicated with each successfully completed phase. There are many other SHIP participant requirements, including certified personnel security, systems cybersecurity protection, U.S.-based operations, etc.

In the SHIP effort, two physical locations are envisioned: a design center (DC) and a manufacturing center (designated assembly and test center, or ATC). Both digital and RF designs will be undertaken. Initial operational capability is targeted for two years, and functional operational capability (full production) is targeted for four years.

The technology driver for this SHIP effort is heterogeneous integration: assembling different functional die on a single substrate and replacing individual components now mounted on circuit boards. Significant reductions in size, weight, and power (SWaP) are expected. Both silicon interposers and organic substrates are to be demonstrated in the SHIP effort.

Further columns are planned based on progress reports from these two DoD electronics packaging efforts.

Reference
1. “Strategic and Spectrum Missions Advanced Resilient Trusted Systems (S2MARTS): Request for Solutions (RFS) in Support of the Very High-Density Interconnect (VHDI) Prototype Project (Project No. S 2 MARTS 19-04),” National Security Technology Accelerator (NSTXL).

Dennis Fritz was a 20-year direct employee of MacDermid Inc. and has just retired after 12 years as a senior engineer at (SAIC) supporting the Naval Surface Warfare Center in Crane, Indiana. He was elected to the IPC Hall of Fame in 2012.