3 Key Takeaways: Understanding the Promise and Practical Limits of ELIC

Estimated reading time: 3 minutes

As semiconductor packages become smaller and more complex, PCB designers face increasing pressure to accommodate higher interconnect densities within tighter space constraints. Every layer interconnect (ELIC) technology offers a way to overcome some of the limitations of traditional HDI construction, but achieving greater density introduces new challenges in fabrication, reliability, and cost.

In his white paper, ELIC: Every Layer Interconnect—The Promise, the Pain, and the Practical Limits, American Standard Circuits (ASC) President and CEO Anaya Vardya examines the advantages of ELIC architecture, the manufacturing challenges that accompany it, and the design decisions that determine whether a board can be produced reliably at scale.

Here are three key takeaways from the paper.

1. ELIC creates more routing space, but greater density comes with trade-offs

Traditional HDI construction relies on mechanical through-holes that occupy valuable board space, even on layers where those connections are unnecessary. ELIC replaces these structures with laser-drilled microvias connecting adjacent layers, making every layer available for routing.

The potential benefits are significant. According to Vardya, designs requiring 20 or more layers in conventional multilayer construction can sometimes be achieved in just 12 to 14 layers using ELIC. When combined with semi-additive processes such as SAP or mSAP, ELIC can also support line-and-space geometries below 25 microns.

However, greater routing density does not automatically translate into a more manufacturable design. ELIC requires additional sequential lamination cycles, tighter registration tolerances, and more sophisticated process controls.

The important distinction is between what can be fabricated under ideal conditions and what can be produced consistently. Designers must evaluate whether the density advantages justify the added manufacturing complexity.

2. Small manufacturing variations can become major reliability problems

One of the greatest challenges in ELIC fabrication is that errors accumulate across successive build-up cycles. Registration shifts, incomplete microvia filling, and repeated thermal exposure can create problems that become increasingly difficult to detect and correct as additional layers are added.

The paper illustrates how a registration shift of just 15 microns can reduce a microvia capture pad's annular ring from 25 to 10 microns, significantly increasing the risk of breakout. What might be an acceptable variation in conventional HDI can become a serious reliability concern in a densely packed ELIC structure.

These challenges also affect production yield. Vardya provides an example in which a six-cycle ELIC process operating at 99% yield per cycle achieves approximately 94% cumulative yield before final testing and assembly. Reducing individual cycle yield to 97% brings that cumulative figure below 84%.

The takeaway is that ELIC reliability depends on maintaining precise control throughout the entire fabrication sequence. Microvia fill quality, registration accuracy, and material stability must be managed at every stage rather than evaluated only in the finished board.

3. Design for manufacturing must begin before the layout is finalized

ELIC requires a closer relationship between PCB design and fabrication than conventional HDI. Decisions involving via stacking, solder mask definition, dielectric thickness, and thermal management can directly affect whether a design is practical to manufacture.

The paper identifies several common mistakes, including applying minimum process geometries throughout a design, carrying traditional HDI via-stacking rules into deeper ELIC structures, and treating solder mask as a finishing consideration rather than a critical design parameter.

ASC recommends using staggered microvias as the production-stable default, reserving stacked structures for areas where routing density makes them necessary. Designers should also preserve additional manufacturing margin in less demanding areas instead of pushing every feature to the smallest possible dimensions.

Early collaboration with the fabricator is especially important. Understanding actual production capabilities, rather than relying exclusively on published minimum specifications, allows designers to make informed decisions about stackup architecture, tolerances, and material selection.

Ultimately, the paper argues that ELIC is not merely the next step in HDI technology. It represents a different approach to PCB design and manufacturing, one in which density, reliability, yield, and cost are closely interconnected. Its greatest advantages emerge when designers understand both what the technology makes possible and what it takes to consistently manufacture those designs.

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