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Editor’s note: This is the second part of an article series on every layer interconnect. Read part one here.
The transition from HDI to every layer interconnect (ELIC) is where the DFM gap between design intent and fabrication reality is most visible. Several common misconceptions appear consistently in the data packages we review at ASC.
The most common ELIC design mistake mirrors what we generally see in first-time UHDI builds: using process minimums everywhere because they appear on a capability chart. In ELIC, this is especially consequential. If only one region truly requires aggressive geometry, say, a fine-pitch BGA escape, the rest of the design should preserve margin. Relaxing non-critical areas makes the overall build more manufacturable without sacrificing the dense region that drives the stackup.
Production capability charts reflect what is achievable under controlled conditions. Production introduces material variation, panel movement, plating distribution effects, and statistical process spread. ELIC compresses those windows. Small adjustments, such as widening a via capture pad by a few microns or relaxing a mask dam in a non-critical area, can shift a build from marginal to stable.
Via Stacking Rules That Do Not Transfer From HDI
Designers who have mastered HDI sometimes carry stacking rules into ELIC without recognizing that aspect ratio and fill requirements change with each additional level. A microvia correctly sized for a two-level stack may not achieve equivalent fill quality in a four-level stack. The target pad must be larger to account for positional uncertainty across multiple build cycles.
The 1:1 aspect ratio guideline is the foundational anchor: a 50 µm via requires an approximately 50 µm dielectric. This relationship affects impedance control, copper thickness, lamination cycles, and long-term reliability simultaneously.
Designers often miss the guidance that if a design terminates multiple ELIC via structures on external layers, the UHDI circuitry should be moved to internal layers. External layers carry the greatest cumulative registration uncertainty from the full build sequence, and placing multiple via terminations there compounds both the registration risk and the solder mask complexity.
To continue reading this article, which originally appeared in the July 2026 I-Connect007 Magazine, click here.
