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Advanced Electronics Packaging Digest

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DFM Mistakes Designers Make When Moving to ELIC

07/20/2026 | Anaya Vardya, American Standard Circuits
The transition from HDI to every layer interconnect (ELIC) is where the DFM gap between design intent and fabrication reality is most visible. Several common misconceptions appear consistently in the data packages we review at ASC. The most common ELIC design mistake mirrors what we generally see in first-time UHDI builds: using process minimums everywhere because they appear on a capability chart. In ELIC, this is especially consequential. If only one region truly requires aggressive geometry, say, a fine-pitch BGA escape, the rest of the design should preserve margin. Relaxing non-critical areas makes the overall build more manufacturable without sacrificing the dense region that drives the stackup.

NCAB Posts Strongest EcoVadis Score Yet in 2026

07/08/2026 | NCAB
NCAB announced its highest EcoVadis result to date, earning an overall score of 79 out of 100, up from 73 in its previous assessment.

Beyond Design: Skip-layer Routing—The Waveguide Structure That Makes 224G Possible

07/09/2026 | Barry Olney -- Column: Beyond Design
As data rates climb from 112G PAM4 toward 224G PAM4 and beyond, electronics designers are discovering that traditional stripline and microstrip geometries are no longer sufficient. The physics simply break. Rise times are now in the single‑digit picosecond range, loss budgets are measured in millimeters, and even tiny discontinuities can collapse a PAM4 eye.

Key Considerations When Selecting an Aqueous Cleaning Agent

06/03/2026 | Adam Klett, Ph.D, KYZEN Corporation
Selecting the appropriate aqueous cleaning agent is one of the most consequential decisions in mitigating contamination risks in high-density designs. Highly dense electronic assemblies have introduced a new level of sensitivity to contamination. Reduced conductor spacing, bottom-terminated components, and elevated power densities significantly increase the risk that even minimal flux residues will lead to electrochemical migration, leakage currents, and long-term reliability failures.

System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor

05/14/2026 | Chetan Arvind Patil, Marvell Technology
In conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.
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