Siemens Collaborates with TSMC to Advance AI for Semiconductor Design

Estimated reading time: 3 minutes

Siemens announced the continuation of collaboration with TSMC to drive innovation in AI-powered automation and advanced semiconductor design enablement. Building on the prior partnership achievements, Siemens is expanding support across the EDA workflow - from automated fixing of design rule violation to certified solutions for leading-edge process technologies.

“Our continued collaboration with TSMC exemplifies Siemens’ commitment to delivering AI-driven automation and advanced semiconductor design capabilities that accelerate our customers’ ability to innovate at the most advanced process nodes,” said Ankur Gupta, executive vice president, EDA IC Software, Siemens Digital Industries Software. “By combining our AI innovations with TSMC’s leading-edge process technologies, we’re helping customers reach new levels of speed, accuracy and design confidence.”

“TSMC greatly values our longstanding partnership with Siemens, a key member of our Open Innovation Platform® (OIP) ecosystem, as we work together to enable next generation semiconductor designs,” said Aveek Sarkar, director of the ecosystem and alliance management division at TSMC. “Through joint advancements in AI-powered EDA tools and certified design enablement, we continue to help customers achieve exceptional results on our latest technologies while driving energy-efficient chip innovation, paving the way for advancements in the semiconductor industry during this transformative era of AI.”

AI-powered chip design solution

Siemens is collaborating with TSMC to advance AI-powered automation across EDA workflows using the recently launched Fuse™ EDA AI System, a comprehensive domain-scoped agentic AI system for semiconductor. Through this collaboration, TSMC is working with Siemens to enhance productivity in custom integrated circuit (IC) design to enable multi-step, multi-tool automations for DRC-centric physical verification with Siemens’ Calibre® software, and to help designers quickly access design information, receive guided recommendations and have real-time command execution to accelerate digital design cycles with Siemens’ Aprisa™ software.

3D IC design solution and TSMC 3DFabric

For TSMC 3DFabric® technologies, Calibre 3DStack supports the interface check flow for alignment and connectivity verification, the inter-chiplet DRC flow for performing 3D-aware DRC validation on the interposers, the inter-chiplet antenna flow for performing antenna analysis on 3D systems and the 3DPERC flow for performing point-to-point (P2P) resistance extraction and current density analysis on 3D systems. These flows are supported in the 3Dblox syntax.

Calibre 3DThermal supports evaluation of thermal impacts on die level designs in the context of 3D IC stacking and has achieved TSMC certification for both static and transient thermal analysis. This means designers can analyze thermal impacts on complex 3D IC products along with complex power deliveries using Calibre 3DThermal to make informed design decisions.

Advanced node technology enablement

Siemens and TSMC are also collaborating on the next generation process node enablement. Siemens’ Calibre nmPlatform software has achieved certification for TSMC’s 3nm, 2nm, A16 and A14 process technologies. The Solido Simulation Suite software is also now certified for SPICE accuracy in TSMC’s N3A, N2P, A16 and A14 process technologies, enabling customers to create and reliably verify analog, mixed-signal, RF, standard cell, and memory designs using advanced TSMC nodes. This collaboration expands into TSMC’s custom design reference flow (CDRF) on its A14 process, as Siemens’ Solido Simulation Suite supports reliability aware simulation technology, which addresses IC aging, real-time self-heating, and Safe Operation Area (SOA) checks. Further, TSMC’s custom design reference flow (CDRF) for its A14 process incorporates Solido Design Environment for advanced variation-aware verification, enhancing design sensitivity and automated cell optimization.

Siemens’ mPower analog is certified for transistor-level EM/IR sign-off for TSMC’s N2P process, underscoring its readiness to support customers’ next-generation designs on TSMC’s advanced nodes. Siemens’ Aprisa software for digital implementation has achieved TSMC N2P Integrated Tool Certification which demonstrates readiness to support advanced node design implementation flow.

Additionally, Siemens tools have been enabled to support customers in the design, implementation, and verification of TSMC Compact Universal Photonic Engine (TSMC-COUPE™) technology. The companies’ joint activity on silicon photonics includes flow development using Siemens’ Innovator3D IC™ software, Calibre 3DStack software, L-Edit software, Solido Simulation Suite software and Calibre Interactive software for design, implementation, and verification of TSMC-COUPE™ technology.​​​​