UHDI, AI, and RF Materials: Signals From the Next Phase of Advanced Packaging
March 11, 2026 | I-Connect007Estimated reading time: 1 minute
The upcoming issue of Advanced Electronics Packaging Digest explores several developments shaping the future of advanced electronics, from the convergence of IC substrates and ultra-high-density interconnect (UHDI) PCBs to the growing influence of artificial intelligence on semiconductor packaging and the materials science behind high-frequency system performance.
In a featured conversation, Jan Pedersen of NCAB examines how the lines between IC substrates and UHDI PCBs are rapidly blurring. Drawing on his presentation, “IC Substrates vs. UHDI PCBs,” from the Pan European Design Conference, Pedersen discusses heterogeneous integration, sub-50-micron manufacturing realities, and the global investment pressures driving new approaches to advanced packaging. His perspective highlights why traditional HDI roadmaps may no longer be sufficient as the industry moves toward increasingly complex system architectures.
Another feature highlights insights from the Global Electronics Association’s Executive Pulse webinar series, where Dr. Hemanth Dhavaleswarapu of AMD explores how the rapid rise of artificial intelligence is reshaping semiconductor technology. As AI workloads scale, packaging has become central to enabling continued performance improvements, influencing everything from chip architecture to the design of hyperscale data centers.
Rounding out the issue, Chandra Gupta of Remtec presents the second installment of his series on ceramic substrates for RF, microwave, and millimeter-wave applications. Building on the fundamentals introduced previously, Gupta examines how interconnect design, circuit architecture, and system integration ultimately determine signal performance at high frequencies.
Together, these features provide a multidimensional view of the technological and engineering forces shaping the next generation of electronic systems.
Don’t miss the upcoming issue of Advanced Electronics Packaging Digest for timely insight into the materials, architectures, and industry dynamics shaping advanced packaging today.
Subscribe to get the latest issue delivered to your inbox here. Subscribe via Substack here.
Subscribe
Stay ahead of the technologies shaping the future of electronics with our latest newsletter, Advanced Electronics Packaging Digest. Get expert insights on advanced packaging, materials, and system-level innovation, delivered straight to your inbox.
Subscribe now to stay informed, competitive, and connected.
Suggested Items
MacDermid Alpha to Address Silver Price Volatility Solutions at ECTC 2026
05/15/2026 | MacDermid AlphaAs volatile silver prices continue to place pressure on semiconductor packaging costs and supply chain predictability, MacDermid Alpha Electronics Solutions will highlight material strategies that help manufacturers reduce dependence on silver without sacrificing reliability, thermal performance, or manufacturing efficiency.
What Heterogeneous Integration Means for EMS Providers
05/14/2026 | Nolan Johnson, I-Connect007Dr. Ravi Mahajan, an Intel Fellow and Director of Intel’s Technology and Pathfinding group, delivered a keynote at the APEX EXPO 2026 technical conference on using heterogeneous integration (HI) as a strategy and on how advanced packaging technology serves as the technical apex for implementing that strategy. Mahajan’s previous papers and industry presentations on such topics as interconnect density, signal integrity, power delivery, thermal path, and assembly yield as system-level constraints confirm him as an expert on package optimization.
System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor
05/14/2026 | Chetan Arvind Patil, Marvell TechnologyIn conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.
I-Connect007 Announces Upcoming Issue of Advanced Electronics Packaging Digest
05/13/2026 | I-Connect007The next issue of Advanced Electronics Packaging Digest examines the materials, architectures, and integration strategies shaping the next phase of electronics innovation, from reinforcement materials under thermal and frequency pressure to heterogeneous integration and advanced packaging as a system-level scaling factor.
ASE, WUS Announce Strategic Collaboration to Build Advanced AI Packaging Hub in Kaohsiung
05/08/2026 | ASE GroupAdvanced Semiconductor Engineering, Inc. (ASE) and WUS Printed Circuit Co., Ltd. (WUS) announced today a strategic collaboration for the construction of a state-of-the-art manufacturing facility in the Nanzih Technology Industrial Park, Kaohsiung.