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Power delivery on modern systems is an important and challenging problem facing hardware designers. These challenges are even more apparent as device operating speeds and current demands increase. Modern FPGAs, processors, and other devices feature fast switching currents and demand precise voltage levels.
Engineers often focus on discrete decoupling capacitors placed near the switching devices in hopes of providing the required capacitance for these high current demands. One of the more overlooked items of the power distribution system is the capacitance formed by the power plane cavities, and how it contributes to the power distribution system’s ability to decouple the switching devices. Through a series of simple simulation experiments, this article will demonstrate a basic principle regarding the effectiveness of the capacitance formed by PCBs.
Basic PDN Model
A basic power delivery network (PDN) includes the voltage regulator model (VRM), the discrete decoupling capacitors, the power plane cavities, and any on-die capacitance formed on the ICs or devices themselves.
The edge rate of this switching current is extremely important when trying to calculate how effective the PDN will be in suppressing the ripple voltage. A traditional method of estimating these currents is to simulate the I/O and look at the driver current spectrum to better understand the switching activity of these devices.1 From this frequency spectrum, one can gain a better understanding of the load dynamics, and how to gauge the effective decoupling radius.
To continue reading this article, which originally appeared in the November 2025 edition of Design007 Magazine, click here.
