The Marketing Minute: If Your Marketing Budget Gets Cut in Half, Then What?
Punching Out: How Are the Big Boys in Electronics Doing?
It’s Only Common Sense: Complexity Is the Enemy of Profit
Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox Standard
April 27, 2023 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc. announced new design flows based on the Cadence® Integrity™ 3D-IC platform to support the TSMC 3Dblox™ standard for 3D front-end design partitioning in complex systems. Through this latest collaboration, the Cadence flows are optimized for all of TSMC’s latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC® ) technologies. By using these design flows, customers can accelerate the development of advanced multi-die package designs for emerging 5G, AI, mobile, hyperscale computing and IoT applications.
The Cadence Integrity 3D-IC platform combines system planning, packaging, and system-level analysis andis a complete solution certified for use with the TSMC 3DFabric and the 3Dblox 1.5 specification. The flows based on this platform incorporate several new features like 3D routability-driven bump assignment and hierarchical bump resource planning. 3Dblox, which is inherently supported by the Integrity 3D-IC platform, provides a seamless interface for Cadence system analysis tools for early power delivery network (PDN) and thermal analysis via the Cadence Voltus™ IC Power Integrity Solution and Celsius™ Thermal Solver system analysis tools; extraction and static timing analysis via the Cadence Quantus™ Extraction Solution and Tempus™ Timing Signoff Solution; and system-level layout versus schematic (LVS) checks via the Cadence Pegasus™ Verification System.
“3D-IC technology is key to meeting the performance, physical size, and power consumption requirements to enable next-generation HPC and mobile applications,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “By continuing our collaboration with Cadence, we’re enabling customers to leverage our comprehensive 3DFabric technologies and the Cadence flows that support our 3Dblox standard, so they can significantly improve 3D-IC design productivity and speed time to market.”
“The Cadence flows based on the Integrity 3D-IC platform incorporate everything a customer needs to quickly design a leading-edge 3D-IC using TSMC’s latest 3DFabric technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “Through our extensive work with TSMC, we’re jointly resolving the 3D-IC design challenges our customers regularly face, putting them on an accelerated path to bring innovative designs to life.”
Share on:
Subscribe
Stay ahead of the technologies shaping the future of electronics with our latest newsletter, Advanced Electronics Packaging Digest. Get expert insights on advanced packaging, materials, and system-level innovation, delivered straight to your inbox.
Subscribe now to stay informed, competitive, and connected.
Suggested Items
New Book Explores How UV Technology Is Transforming Electronics Protection, Efficiency, and Sustainability
05/14/2026 | I-Connect007I-Connect007 proudly announces the recent release of The Printed Circuit Designer’s Guide to…™ UV Curable Conformal Coatings. Authored by respected industry technologists Brian Chislea and Cody Schoener, PhD, of Dow, Inc., this new volume offers a comprehensive exploration of UV-curable conformal coatings and their expanding role in improving the protection, performance, and sustainability of electronic assemblies.
Siemens Expands EDA Software Access Through EuroCDP Project
05/14/2026 | SiemensSiemens has become the first software provider to sign a strategic framework agreement with the European Chips Joint Undertaking (Chips JU) which aims to bolster Europe's semiconductor industry by fostering collaboration between the EU, member states and the private sector, through the European Chips Design Platform (EuroCDP) project.
Rethinking Stackup, Materials, and Tolerances in Modern Designs
05/14/2026 | Kristin Moyer, Global Electronics AssociationThe simple rectangular rigid PCB is becoming increasingly infrequent. This reality necessitates designing with concepts well outside traditional rigid PCB methodologies. For example, the designer of wearable electronics may need to implement conductive fibers integrated into the textile material. Heads-up displays, like those in VR/AR headsets and glasses, require transparent circuitry etched into the display glass. The process of designing without a rule book usually starts with something other than the traditional board design process.
New Courses: Advance Your Electronics Expertise in June and July
05/14/2026 | Global Electronics AssociationStay current with design, manufacturing, and quality standards by enrolling in one of these online instructor-led courses starting in June and July from ElectronicsU at the Global Electronics Association, designed to help professionals at every level sharpen their skills and advance their careers. These live, expert-led sessions combine flexibility with real-time interaction, allowing participants to learn directly from seasoned industry professionals while collaborating with peers worldwide. Access to all applicable IPC standards is included in the courses.
Road to Reliability: Engineering High Uptime EV Charging Infrastructure
05/13/2026 | Stanton Rak, SF Rak CompanyThe transition to EVs is no longer constrained solely by vehicle capability. Instead, it is increasingly defined by a simpler, but more unforgiving question: Will the charger work when I arrive? This high uptime does not happen by accident. As EV technology has matured, limitations in battery range, power electronics, and thermal management are no longer the primary barriers to adoption.