The Chemical Connection: Surface Finishes for PCBs
It’s Only Common Sense: 7 Tips to Focus on What Works
The Marketing Minute: Go Big or Go Home—Long-form Content Is Your Brand’s Best Friend
PCB Surface Topography and Copper Balancing Under Large Form Factor BGAs
October 1, 2024 | Neil Hubble, Akrometrix and Gary A. Brist, Intel CorporationEstimated reading time: 1 minute
Editor’s Note: This paper was originally published in the Proceedings of IPC APEX EXPO 2024.
Background
As CPU and GPU packages grow larger and contain higher pin/ball counts, the importance of managing the printed circuit board (PCB) surface coplanarity for package assembly increases. The PCB surface coplanarity under a package is a product of both the global bow/twist of the PCB and the local surface topography under the package. In general, the surface topography is dependent the choice of material and layer stackup and the interaction between the innerlayer copper patterns and prepreg resin flow.
Advances in chiplet design and heterogeneous integration solutions in electronic packaging are enabling complex packages with increasing total die areas, resulting in the need for larger CPU and GPU packages1. Based on trends and advances in package integration, it is expected that future packages exceeding 100–120 mm on a package edge will become more common. This increases the challenge of the second-level interconnect (SLI) assembly processes when attaching the package to the PCB due to the combined coplanarity and topography variations of the PCB and package. These combined influences between the PCB and package are the key drivers of SLI defects such as solder bridging or solder joint opens during PCB assembly.2,3 Figure 1 is a graphical depiction of how the global PCB warpage or curvature under the package must be smaller for larger packages to achieve the same PCB coplanarity under the package.
Figure 1: PCB coplanarity under package.
The characterization of PCB coplanarity under the package footprint has been studied historically, including influences of assembly temperatures on dynamic PCB coplanarity as the PCB and package move together through the assembly reflow temperature profile.4,5,6 Other works have shown how the choice of PCB materials, fabrication process conditions, and design each impact global PCB bow/twist and warpage7.
To continue reading this article, which originally published in the September 2024 SMT007 Magazine, click here.
Share on:
Suggested Items
Real Time with... IPC APEX EXPO 2025: New Dispensing and Coating Solutions
04/03/2025 | Real Time with...IPC APEX EXPOMichael Hanke, Global Sales Officer at Rehm, discusses new dispensing and coating equipment developed in Germany. He emphasizes the significance of software integration with customer systems to tackle market challenges.
Real Time with... IPC APEX EXPO 2025: Maximizing Cost Savings in PCB Design With NCAB
04/02/2025 | Real Time with...IPC APEX EXPOKelly Dack and Lonnie Port discuss NCAB's role in the printed circuit board industry. With 30 years of experience, NCAB emphasizes the importance of customer involvement during the design process to achieve significant cost reductions.
'Let’s Talk Production Test' with Bert Horner of The Test Connection, Inc. at SMTA Long Island Meeting
04/02/2025 | The Test Connection Inc.The Test Connection Inc. (TTCI), a leading provider of electronic test and manufacturing solutions, is pleased to announce that its President, Bert Horner, will present at the SMTA Long Island Chapter Technical Meeting & Dinner on Wednesday, April 16, 2025. The event will take place at the Radisson Hotel Hauppauge in Hauppauge, NY.
CEE PCB Appoints Markus Voeltz to Business Development Director Europe
04/02/2025 | CEE PCBCEE PCB, a leading manufacturer of printed circuit boards (PCBs) and flexible printed circuits (FPCs) with 3 production facilities in China, is expanding its presence in Europe and began providing local support in March 2025. With 25 years of experience in the industry, the company is enhancing its commitment to European customers by providing more direct collaboration for technical inquiries and advice.
BEST Inc. Presents StencilQuik for Simplifying BGA Rework Challenges
04/02/2025 | BEST Inc.BEST Inc., a leader in electronic component rework services, training, and rework tools is thrilled to announce StencilQuik™ rework stencils. This innovative product is specifically designed for placing Ball Grid Arrays (BGAs) or Chip Scale Packages (CSPs) during the rework process.