Knocking Down the Bone Pile: Revamp Your Components with BGA Reballing
SMT Perspectives & Prospects: Artificial Intelligence Part 6: Data Module 1
Standard of Excellence: Overcoming Service Failures—The Art of the Apology
Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox Standard
April 27, 2023 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc. announced new design flows based on the Cadence® Integrity™ 3D-IC platform to support the TSMC 3Dblox™ standard for 3D front-end design partitioning in complex systems. Through this latest collaboration, the Cadence flows are optimized for all of TSMC’s latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC® ) technologies. By using these design flows, customers can accelerate the development of advanced multi-die package designs for emerging 5G, AI, mobile, hyperscale computing and IoT applications.
The Cadence Integrity 3D-IC platform combines system planning, packaging, and system-level analysis andis a complete solution certified for use with the TSMC 3DFabric and the 3Dblox 1.5 specification. The flows based on this platform incorporate several new features like 3D routability-driven bump assignment and hierarchical bump resource planning. 3Dblox, which is inherently supported by the Integrity 3D-IC platform, provides a seamless interface for Cadence system analysis tools for early power delivery network (PDN) and thermal analysis via the Cadence Voltus™ IC Power Integrity Solution and Celsius™ Thermal Solver system analysis tools; extraction and static timing analysis via the Cadence Quantus™ Extraction Solution and Tempus™ Timing Signoff Solution; and system-level layout versus schematic (LVS) checks via the Cadence Pegasus™ Verification System.
“3D-IC technology is key to meeting the performance, physical size, and power consumption requirements to enable next-generation HPC and mobile applications,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “By continuing our collaboration with Cadence, we’re enabling customers to leverage our comprehensive 3DFabric technologies and the Cadence flows that support our 3Dblox standard, so they can significantly improve 3D-IC design productivity and speed time to market.”
“The Cadence flows based on the Integrity 3D-IC platform incorporate everything a customer needs to quickly design a leading-edge 3D-IC using TSMC’s latest 3DFabric technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “Through our extensive work with TSMC, we’re jointly resolving the 3D-IC design challenges our customers regularly face, putting them on an accelerated path to bring innovative designs to life.”
Share on:
Testimonial
"The I-Connect007 team is outstanding—kind, responsive, and a true marketing partner. Their design team created fresh, eye-catching ads, and their editorial support polished our content to let our brand shine. Thank you all! "
Sweeney Ng - CEE PCBSuggested Items
Cadence Giving Foundation Announces Multi-Year Commitment to Expand the AI Hub at San José State University
10/13/2025 | Cadence Design Systems, Inc.The Cadence Giving Foundation today announced a multi-year commitment to expand the AI Hub at San José State University (SJSU) to equip students with the skills, hands-on training and experience needed to excel in careers in artificial intelligence (AI).
NEDME Returns October 22 — The Northwest’s Premier Design & Manufacturing Expo
10/13/2025 | NEDMEThe Northwest Electronics Design & Manufacturing Expo (NEDME) returns on Wednesday, October 22, 2025, at Wingspan Event & Conference Center, Hillsboro. The event brings together engineers, product designers, manufacturers, educators, and community partners for a full day of industry connection, learning, and networking.
Sumitomo Riko Boosts Automotive Design Efficiency 10x with Ansys AI Simulation Technology
10/13/2025 | SynopsysSumitomo Riko is implementing Ansys, part of Synopsys, Inc. AI technology to accelerate time-to-solution and improve efficiency during the design and manufacturing of automotive components.
Beyond the Board: Early Engagement Means Faster Prototyping for Defense Programs
10/14/2025 | Jesse Vaughan -- Column: Beyond the BoardIn the defense electronics sector, speed-to-market has shifted from being a commercial differentiator to a national security imperative. The ability to move from design concept to deployable system in months rather than years can provide the U.S. with important strategic advantages. Prototyping, once regarded as a costly and optional stage, has become the linchpin for accelerating program schedules while safeguarding performance, compliance, and mission reliability.
Si2 Names NVIDIA, Synopsys Technologists to Lead New LLM Benchmarking Coalition
10/10/2025 | BUSINESS WIREThe Silicon Integration Initiative today announced the chair and vice chair of the Si2 Large Language Model Benchmarking Coalition (LBC), a collaborative industry initiative and standards body advancing AI for silicon design and verification that will expedite the development of high-quality large language models for semiconductor design problems.